openmv/tools/st/cubeprog/Data_Base/STM32_Prog_DB_0x44D.xml
iabdalkader f9ee15bf46 tools/st: Add cubeprog.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
2025-02-11 17:22:20 +01:00

872 lines
30 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
<Device>
<DeviceID>0x44D</DeviceID>
<Vendor>STMicroelectronics</Vendor>
<Type>MCU</Type>
<!-- cortex written in word file +mpu should it be written?? -->
<CPU>Cortex-M0+</CPU>
<Name>STM32C09x</Name>
<Series>STM32C0</Series>
<Description>ARM 32-bit Cortex-M0+ based device</Description>
<Configurations>
<!-- JTAG_SWD Interface -->
<Interface name="JTAG_SWD"/>
<!-- Bootloader Interface -->
<Interface name="Bootloader"/>
</Configurations>
<!-- Peripherals -->
<Peripherals>
<!-- Embedded SRAM -->
<Peripheral>
<Name>Embedded SRAM</Name>
<Type>Storage</Type>
<Description/>
<ErasedValue>0x00</ErasedValue>
<Access>RWE</Access>
<!-- 30 KB -->
<Configuration>
<Parameters address="0x20000000" name="SRAM" size="0x7800"/>
<Description/>
<Organization>Single</Organization>
<Bank name="Bank 1">
<Field>
<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x7800"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- Embedded Flash -->
<Peripheral>
<Name>Embedded Flash</Name>
<Type>Storage</Type>
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
<ErasedValue>0xFF</ErasedValue>
<Access>RWE</Access>
<FlashSize address="0x1FFF75A0" default="0x40000"/>
<BootloaderVersion address="0x1FFF17FE"/>
<!-- 256KB -->
<Configuration>
<Parameters address="0x08000000" name=" 256 KB Embedded Flash" size="0x40000"/>
<Description/>
<Organization>Single</Organization>
<Alignment>0x8</Alignment>
<Bank name="Bank 1">
<Field>
<Parameters address="0x08000000" name="sector0" occurrence="0x80" size="0x800"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- OTP -->
<Peripheral>
<Name>OTP</Name>
<Type>Storage</Type>
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
<ErasedValue>0xFF</ErasedValue>
<Access>RW</Access>
<!-- 1 KBytes single bank -->
<Configuration>
<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
<Description/>
<Organization>Single</Organization>
<Alignment>0x4</Alignment>
<Bank name="OTP">
<Field>
<Parameters address="0x1FFF7000" name="OTP" occurrence="0x1" size="0x400"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- Option Bytes -->
<Peripheral>
<Name>Option Bytes</Name>
<Type>Configuration</Type>
<Description/>
<Access>RW</Access>
<Bank interface="JTAG_SWD">
<Parameters address="0x40022020" name="Bank 1" size="0x64"/>
<Category>
<Name>Read Out Protection</Name>
<Field>
<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>RDP</Name>
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0xAA">Level 0, no protection</Val>
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
<Val value="0xCC">Level 2, chip protection</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>BOR Level</Name>
<Field>
<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
<AssignedBits>
<Bit>
<Name>BOR_EN</Name>
<Description/>
<BitOffset>0x8</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
</Values>
</Bit>
<Bit>
<Name>BORR_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0x9</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR falling level 1 with threshold around 2.1 V</Val>
<Val value="0x1">BOR falling level 2 with threshold around 2.3 V</Val>
<Val value="0x2">BOR falling level 3 with threshold around 2.6 V</Val>
<Val value="0x3">BOR falling level 4 with threshold around 2.9 V</Val>
</Values>
</Bit>
<Bit>
<Name>BORF_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0xB</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR rising level 1 with threshold around 2.0 V</Val>
<Val value="0x1">BOR rising level 2 with threshold around 2.2 V</Val>
<Val value="0x2">BOR rising level 3 with threshold around 2.5 V</Val>
<Val value="0x3">BOR rising level 4 with threshold around 2.8 V</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>User Configuration</Name>
<Field>
<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>nRST_STOP</Name>
<Description/>
<BitOffset>0xD</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Stop mode</Val>
<Val value="0x1">No reset generated when entering Stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_STDBY</Name>
<Description/>
<BitOffset>0xE</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Standby mode</Val>
<Val value="0x1">No reset generated when entering Standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_SHDW</Name>
<Description/>
<BitOffset>0xF</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_SW</Name>
<Description/>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware independent watchdog</Val>
<Val value="0x1">Software independent watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STOP</Name>
<Description/>
<BitOffset>0x11</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
<Val value="0x1">IWDG counter active in stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STDBY</Name>
<Description/>
<BitOffset>0x12</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
<Val value="0x1">IWDG counter active in standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>WWDG_SW</Name>
<Description/>
<BitOffset>0x13</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware window watchdog</Val>
<Val value="0x1">Software window watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>HSE_NOT_REMAPPED</Name>
<Description/>
<BitOffset>0x15</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">HSE_NOT_REMAPPED enable</Val>
<Val value="0x1">HSE_NOT_REMAPPED disable</Val>
</Values>
</Bit>
<Bit>
<Name>RAM_PARITY_CHECK</Name>
<Description/>
<BitOffset>0x16</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">RAM_PARITY_CHECK enable</Val>
<Val value="0x1">RAM_PARITY_CHECK disable</Val>
</Values>
</Bit>
<Bit>
<Name>SECURE_MUXING_EN</Name>
<Description/>
<BitOffset>0x17</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SECURE_MUXING_EN disable </Val>
<Val value="0x1">SECURE_MUXING_EN enable</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT_SEL</Name>
<Description/>
<BitOffset>0x18</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 pin (legacy mode)</Val>
<Val value="0x1">nBOOT0 option bit </Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT1</Name>
<Description/>
<BitOffset>0x19</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1</Val>
<Val value="0x1">Boot from Flash if BOOT0 = 1, otherwise system memory</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT0</Name>
<Description/>
<BitOffset>0x1A</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">nBOOT0=0</Val>
<Val value="0x1">nBOOT0=1</Val>
</Values>
</Bit>
<Bit>
<Name>NRST_MODE</Name>
<Description/>
<BitOffset>0x1B</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reserved</Val>
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
</Values>
</Bit>
<Bit>
<Name>IRHEN</Name>
<Description>Internal reset holder enable bit</Description>
<BitOffset>0x1D</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>PCROP Protection</Name>
<Field>
<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1A_STRT</Name>
<Description>Start offset of first PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1A_END</Name>
<Description>End offset of first PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000200"/>
</Bit>
<Bit>
<Name>PCROP_RDP</Name>
<Description/>
<BitOffset>0x1F</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">PCROP zone is kept when RDP is decreased; Partial Mass Erase done</Val>
<Val value="0x1">PCROP zone is erased when RDP is decreased Full Mass Erase done</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022034" name="FLASH_PCROP1BSR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1B_STRT</Name>
<Description>Start offset of second PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022038" name="FLASH_PCROP1BER" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1B_END</Name>
<Description>End offset of second PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000200"/>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>Write Protection</Name>
<Field>
<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1A_STRT</Name>
<Description>TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1A_END</Name>
<Description>End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1B_STRT</Name>
<Description>Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1B_END</Name>
<Description>End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
</Category>
<!--</Bank>
<Bank interface="JTAG_SWD">
<Parameters address="0x40022080" name="Bank 2" size="0x10"/>-->
<Category>
<Name>FLASH security</Name>
<Field>
<Parameters address="0x40022080" name="FLASH_SECR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>SEC_SIZE</Name>
<Description>Securable memory area size</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>BOOT_LOCK</Name>
<Description>Used to force boot from user area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
<Val value="0x1">Boot forced from Main Flash memory</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
</Bank>
<Bank interface="Bootloader">
<Parameters address="0x1FFF7800" name="Bank 1" size="0x74"/>
<Category>
<Name>Read Out Protection</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>RDP</Name>
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0xAA">Level 0, no protection</Val>
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
<Val value="0xCC">Level 2, chip protection</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>BOR Level</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>BOR_EN</Name>
<Description/>
<BitOffset>0x8</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
</Values>
</Bit>
<Bit>
<Name>BORR_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0x9</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR falling level 1 with threshold around 2.1 V</Val>
<Val value="0x1">BOR falling level 2 with threshold around 2.3 V</Val>
<Val value="0x2">BOR falling level 3 with threshold around 2.6 V</Val>
<Val value="0x3">BOR falling level 4 with threshold around 2.9 V</Val>
</Values>
</Bit>
<Bit>
<Name>BORF_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0xB</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR rising level 1 with threshold around 2.0 V</Val>
<Val value="0x1">BOR rising level 2 with threshold around 2.2 V</Val>
<Val value="0x2">BOR rising level 3 with threshold around 2.5 V</Val>
<Val value="0x3">BOR rising level 4 with threshold around 2.8 V</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>User Configuration</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>nRST_STOP</Name>
<Description/>
<BitOffset>0xD</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Stop mode</Val>
<Val value="0x1">No reset generated when entering Stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_STDBY</Name>
<Description/>
<BitOffset>0xE</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Standby mode</Val>
<Val value="0x1">No reset generated when entering Standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_SHDW</Name>
<Description/>
<BitOffset>0xF</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_SW</Name>
<Description/>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware independent watchdog</Val>
<Val value="0x1">Software independent watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STOP</Name>
<Description/>
<BitOffset>0x11</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
<Val value="0x1">IWDG counter active in stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STDBY</Name>
<Description/>
<BitOffset>0x12</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
<Val value="0x1">IWDG counter active in standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>WWDG_SW</Name>
<Description/>
<BitOffset>0x13</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware window watchdog</Val>
<Val value="0x1">Software window watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>HSE_NOT_REMAPPED</Name>
<Description/>
<BitOffset>0x15</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">HSE_NOT_REMAPPED enable</Val>
<Val value="0x1">HSE_NOT_REMAPPED disable</Val>
</Values>
</Bit>
<Bit>
<Name>RAM_PARITY_CHECK</Name>
<Description/>
<BitOffset>0x16</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">RAM_PARITY_CHECK enable</Val>
<Val value="0x1">RAM_PARITY_CHECK disable</Val>
</Values>
</Bit>
<Bit>
<Name>SECURE_MUXING_EN</Name>
<Description/>
<BitOffset>0x17</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SECURE_MUXING_EN disable </Val>
<Val value="0x1">SECURE_MUXING_EN enable</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT_SEL</Name>
<Description/>
<BitOffset>0x18</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 pin (legacy mode)</Val>
<Val value="0x1">nBOOT0 option bit </Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT1</Name>
<Description/>
<BitOffset>0x19</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1</Val>
<Val value="0x1">Boot from Flash if BOOT0 = 1, otherwise system memory</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT0</Name>
<Description/>
<BitOffset>0x1A</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">nBOOT0=0</Val>
<Val value="0x1">nBOOT0=1</Val>
</Values>
</Bit>
<Bit>
<Name>NRST_MODE</Name>
<Description/>
<BitOffset>0x1B</BitOffset>
<BitWidth>0x2</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reserved</Val>
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
</Values>
</Bit>
<Bit>
<Name>IRHEN</Name>
<Description>Internal reset holder enable bit</Description>
<BitOffset>0x1D</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>PCROP Protection</Name>
<Field>
<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1A_STRT</Name>
<Description>Start offset of first PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1A_END</Name>
<Description>End offset of first PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000200"/>
</Bit>
<Bit>
<Name>PCROP_RDP</Name>
<Description/>
<BitOffset>0x1F</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">PCROP zone is kept when RDP is decreased Partial Mass Erase done</Val>
<Val value="0x1">PCROP zone is erased when RDP is decreased Full Mass Erase done</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters name="PCROP1BSR" size="0x4" address="0x1FFF7828"/>
<AssignedBits>
<Bit>
<Name>PCROP1B_STRT</Name>
<Description>Start offset of second PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters name="PCROP1BER" size="0x4" address="0x1FFF7830"/>
<AssignedBits>
<Bit>
<Name>PCROP1B_END</Name>
<Description>End offset of second PCROP zone in bank 1</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x9</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x200" offset="0x08000200"/>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>Write Protection</Name>
<Field>
<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1A_STRT</Name>
<Description>Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1A_END</Name>
<Description>End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1B_STRT</Name>
<Description>Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1B_END</Name>
<Description>End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
</Category>
<!--</Bank>
<Bank interface="Bootloader">
<Parameters address="0x1FFF7870" name="Bank 2" size="0x4"/>-->
<Category>
<Name>FLASH security</Name>
<Field>
<Parameters address="0x1FFF7870" name="FLASH_SECR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>BOOT_LOCK</Name>
<Description>Used to force boot from user area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
<Val value="0x1">Boot forced from Main Flash memory</Val>
</Values>
</Bit>
<Bit>
<Name>SEC_SIZE</Name>
<Description>Securable memory area size</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x7</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
</Category>
</Bank>
</Peripheral>
</Peripherals>
</Device>
</Root>