mirror of
https://github.com/openmv/openmv.git
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1236 lines
44 KiB
XML
1236 lines
44 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x467</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<!-- cortex written in word file +mpu should it be written?? -->
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<CPU>Cortex-M0+</CPU>
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<Name>STM32G0B0xx/B1xx/C1xx</Name>
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<Series>STM32G0</Series>
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<Description>ARM 32-bit Cortex-M0+ based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<!-- 512kB Single Bank-->
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<Configuration number="0x0">
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<DualBank>
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<ReadRegister address="0x40022020" mask="0x200000" value="0x0"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="200"/>
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</FlashSize>
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</Configuration>
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<!-- 512kB dual Bank-->
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<Configuration number="0x1">
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<DualBank>
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<ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="200"/>
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</FlashSize>
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</Configuration>
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<!-- 256 Single Bank-->
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<Configuration number="0x2">
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<DualBank>
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<ReadRegister address="0x40022020" mask="0x200000" value="0x0"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="100"/>
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</FlashSize>
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</Configuration>
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<!-- 256 Dual Bank-->
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<Configuration number="0x3">
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<DualBank>
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<ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="100"/>
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</FlashSize>
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</Configuration>
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<!-- 128 Single Bank-->
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<Configuration number="0x4">
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="80"/>
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</FlashSize>
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<!-- 512kB Single Bank-->
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<Configuration number="0x0">
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<DualBank>
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<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x0"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="200"/>
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</FlashSize>
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</Configuration>
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<!-- 512kB dual Bank-->
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<Configuration number="0x1">
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<DualBank>
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<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x200000"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="200"/>
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</FlashSize>
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</Configuration>
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<!-- 256 Single Bank-->
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<Configuration number="0x2">
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<DualBank>
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<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x0"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="100"/>
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</FlashSize>
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</Configuration>
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<!-- 256 Single Bank-->
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<Configuration number="0x3">
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<DualBank>
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<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x200000"/>
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</DualBank>
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="100"/>
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</FlashSize>
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</Configuration>
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<!-- 128 Single Bank-->
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<Configuration number="0x4">
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<FlashSize>
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<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="80"/>
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</FlashSize>
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</Configuration>
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<!-- dummy config -->
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<Configuration number="0x6">
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<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 128KB -->
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<Configuration>
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<Parameters address="0x20000000" name="SRAM" size="0x20000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x20000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x1FFF75E0" default="0x80000"/>
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<BootloaderVersion address="0x1FFF9FFE"/>
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<!-- 512K Single Bank -->
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<Configuration config="0">
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<Parameters address="0x08000000" name=" 512 KB Embedded Flash" size="0x80000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x100" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 512K dual Bank -->
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<Configuration config="1">
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<Parameters address="0x08000000" name=" 512 KB Embedded Flash" size="0x80000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x80" size="0x800"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08040000" name="sector128" occurrence="0x80" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 256K single Bank-->
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<Configuration config="2">
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<Parameters address="0x08000000" name=" 256 KB Embedded Flash" size="0x40000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x80" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 256K dual Bank -->
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<Configuration config="3">
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<Parameters address="0x08000000" name=" 256 KB Embedded Flash" size="0x40000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x40" size="0x800"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08020000" name="sector64" occurrence="0x40" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 128K Single Bank-->
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<Configuration config="4">
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<Parameters address="0x08000000" name=" 128 KB Embedded Flash" size="0x020000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x40" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- OTP -->
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<Peripheral>
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<Name>OTP</Name>
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<Type>Storage</Type>
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<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 1 KBytes single bank -->
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<Configuration>
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<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="OTP">
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<Field>
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<Parameters address="0x1FFF7000" name="OTP" occurrence="0x1" size="0x400"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Mirror Option Bytes -->
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<Peripheral>
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<Name>MirrorOptionBytes</Name>
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<Type>Storage</Type>
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<Description>Mirror Option Bytes contains the extra area.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 56 Bytes Dual bank -->
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<Configuration>
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<Parameters address="0x1FFF7800" name=" 56 Bytes Data MirrorOptionBytes" size="0x38"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x1FFF7800" name="Bank1" occurrence="0x1" size="0x34"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x1FFF7870" name="Bank2" occurrence="0x1" size="0x4"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x40022020" name="Bank 1" size="0x40"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_EN</Name>
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<Description/>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
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<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>BORF_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x9</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
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<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
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<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
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<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>BORR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0xB</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
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<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
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<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
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<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0xD</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated when entering Stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0xE</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated when entering Standby mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_SHDW</Name>
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<Description/>
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<BitOffset>0xF</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
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<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description/>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware independent watchdog</Val>
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<Val value="0x1">Software independent watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description/>
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<BitOffset>0x11</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in stop mode</Val>
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<Val value="0x1">IWDG counter active in stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description/>
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<BitOffset>0x12</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in standby mode</Val>
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<Val value="0x1">IWDG counter active in standby mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>WWDG_SW</Name>
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<Description/>
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<BitOffset>0x13</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware window watchdog</Val>
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<Val value="0x1">Software window watchdog</Val>
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</Values>
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</Bit>
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<Bit config="0,1,2,3">
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<Name>nSWAP_BANK</Name>
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<Description/>
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<BitOffset>0x14</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">nSWAP_BANK = 0, BANK2 is mapped at 0x0800_0000 address : Bank 1 and bank 2 address are swapped</Val>
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<Val value="0x1">nSWAP_BANK = 1, BANK1 is mapped at 0x0800_0000 address : Bank 1 and bank 2 address are not swapped</Val>
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</Values>
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</Bit>
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<Bit config="0,1,2,3">
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<Name>DUAL_BANK</Name>
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<Description/>
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<BitOffset>0x15</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">256 Kbytes/512 Kbytes single-bank Flash memory(contiguous addresses in Bank 1)</Val>
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<Val value="0x1">256 Kbytes/512 Kbytes dual-bank Flash memory</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>RAM_PARITY_CHECK</Name>
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<Description/>
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<BitOffset>0x16</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
|
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<Values>
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<Val value="0x0">SRAM parity check enable</Val>
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<Val value="0x1">SRAM parity check disable</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nBOOT_SEL</Name>
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<Description/>
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<BitOffset>0x18</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
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<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
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</Values>
|
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</Bit>
|
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<Bit>
|
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<Name>nBOOT1</Name>
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<Description/>
|
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<BitOffset>0x19</BitOffset>
|
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
|
|
<Values>
|
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<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
|
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<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
|
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</Values>
|
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</Bit>
|
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<Bit>
|
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<Name>nBOOT0</Name>
|
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<Description/>
|
|
<BitOffset>0x1A</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
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<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">nBOOT0=0</Val>
|
|
<Val value="0x1">nBOOT0=1</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NRST_MODE</Name>
|
|
<Description/>
|
|
<BitOffset>0x1B</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reserved</Val>
|
|
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
|
|
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
|
|
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IRHEN</Name>
|
|
<Description>Internal reset holder enable bit</Description>
|
|
<BitOffset>0x1D</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
|
|
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>PCROP Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1A_STRT</Name>
|
|
<Description>Flash Area A PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1A_END</Name>
|
|
<Description>Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>PCROP_RDP</Name>
|
|
<Description/>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
|
|
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022034" name="FLASH_PCROP1BSR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1B_STRT</Name>
|
|
<Description>Flash Area B PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022038" name="FLASH_PCROP1BER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1B_END</Name>
|
|
<Description>Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022044" name="FLASH_PCROP2SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2A_STRT</Name>
|
|
<Description>Flash Area A PCROP2 start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022048" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2A_END</Name>
|
|
<Description>Flash Area A PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_PCROP1BSR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2B_STRT</Name>
|
|
<Description>Flash Area B PCROP2 start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022058" name="FLASH_PCROP1BER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2B_END</Name>
|
|
<Description>Flash Area B PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
|
|
<Field>
|
|
<Parameters address="0x4002204C" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of the last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of the last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022080" name="Bank 2" size="0x10"/>
|
|
<Category>
|
|
<Name>FLASH security</Name>
|
|
<Field>
|
|
<Parameters address="0x40022080" name="FLASH_SECR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOOT_LOCK</Name>
|
|
<Description>used to force boot from user area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
|
|
<Val value="0x1">Boot forced from Main Flash memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SEC_SIZE</Name>
|
|
<Description>Securable memory for Bank 1 </Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SEC_SIZE2</Name>
|
|
<Description>Securable memory for Bank 2 On Dual Bank device,otherwise reserved </Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFF7800" name="Bank 1" size="0x44"/>
|
|
<Category>
|
|
<Name>Read Out Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>RDP</Name>
|
|
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0xAA">Level 0, no protection</Val>
|
|
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
|
<Val value="0xCC">Level 2, chip protection</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>BOR Level</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_EN</Name>
|
|
<Description/>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
|
|
<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>BORF_LEV</Name>
|
|
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
|
|
<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
|
|
<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
|
|
<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>BORR_LEV</Name>
|
|
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
|
<BitOffset>0xB</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
|
|
<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
|
|
<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
|
|
<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>nRST_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0xD</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
|
<Val value="0x1">No reset generated when entering Stop mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0xE</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
|
<Val value="0x1">No reset generated when entering Standby mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_SHDW</Name>
|
|
<Description/>
|
|
<BitOffset>0xF</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
|
|
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware independent watchdog</Val>
|
|
<Val value="0x1">Software independent watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
|
<Val value="0x1">IWDG counter active in stop mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0x12</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
|
<Val value="0x1">IWDG counter active in standby mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x13</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware window watchdog</Val>
|
|
<Val value="0x1">Software window watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit config="0,1,2,3">
|
|
<Name>nSWAP_BANK</Name>
|
|
<Description/>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">nSWAP_BANK = 0, BANK2 is mapped at 0x0800_0000 address : Bank 1 and bank 2 address are swapped</Val>
|
|
<Val value="0x1">nSWAP_BANK = 1, BANK1 is mapped at 0x0800_0000 address : Bank 1 and bank 2 address are not swapped</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit config="0,1,2,3">
|
|
<Name>DUAL_BANK</Name>
|
|
<Description/>
|
|
<BitOffset>0x15</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">256 Kbytes/512 Kbytes single-bank Flash memory(contiguous addresses in Bank 1)</Val>
|
|
<Val value="0x1">256 Kbytes/512 Kbytes dual-bank Flash memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>RAM_PARITY_CHECK</Name>
|
|
<Description/>
|
|
<BitOffset>0x16</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM parity check enable</Val>
|
|
<Val value="0x1">SRAM parity check disable</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT_SEL</Name>
|
|
<Description/>
|
|
<BitOffset>0x18</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
|
|
<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT1</Name>
|
|
<Description/>
|
|
<BitOffset>0x19</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
|
|
<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT0</Name>
|
|
<Description/>
|
|
<BitOffset>0x1A</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">nBOOT0=0</Val>
|
|
<Val value="0x1">nBOOT0=1</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NRST_MODE</Name>
|
|
<Description/>
|
|
<BitOffset>0x1B</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reserved</Val>
|
|
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
|
|
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
|
|
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IRHEN</Name>
|
|
<Description>Internal reset holder enable bit</Description>
|
|
<BitOffset>0x1D</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
|
|
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>PCROP Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1A_STRT</Name>
|
|
<Description>Flash Area A PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1A_END</Name>
|
|
<Description>Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>PCROP_RDP</Name>
|
|
<Description/>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
|
|
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters name="PCROP1BSR" size="0x4" address="0x1FFF7828"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1B_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters name="PCROP1BER" size="0x4" address="0x1FFF7830"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP1B_END</Name>
|
|
<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000008"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7838" name="FLASH_PCROP2SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2A_STRT</Name>
|
|
<Description>Flash Area A PCROP2 start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7840" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2A_END</Name>
|
|
<Description>Flash Area A PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x200" offset="0x08000200"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters name="PCROP2BSR" size="0x4" address="0x1FFF7858"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2B_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP2 start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters name="PCROP2BER" size="0x4" address="0x1FFF7860"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PCROP2B_END</Name>
|
|
<Description>Flash Bank 2 PCROP2 End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x9</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000008"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7848" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of the last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7850" name="FLASH_WRP1BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of the last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFF7870" name="Bank 2" size="0x4"/>
|
|
<Category>
|
|
<Name>FLASH security</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7870" name="FLASH_SECR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOOT_LOCK</Name>
|
|
<Description>used to force boot from user area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
|
|
<Val value="0x1">Boot forced from Main Flash memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SEC_SIZE</Name>
|
|
<Description>Securable memory for Bank 1 </Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SEC_SIZE2</Name>
|
|
<Description>Securable memory for Bank 2 On Dual Bank device,otherwise reserved </Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Peripheral>
|
|
</Peripherals>
|
|
</Device>
|
|
</Root> |