mirror of
https://github.com/openmv/openmv.git
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2377 lines
88 KiB
XML
2377 lines
88 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x474</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M33</CPU>
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<Name>STM32H50x</Name>
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<Series>STM32H5</Series>
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<Description>ARM 32-bit Cortex-M33 based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<Configuration number="0x0"> <!-- dual Bank non secure -->
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<TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
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</Configuration>
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<Configuration number="0x1"> <!-- Dual Bank secure -->
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<TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
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</Configuration>
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<Configuration number="0x4"> <!-- Empty config to avoid crash -->
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<Configuration number="0x2"> <!-- Dual Bank Secure-->
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<TZEN reference="0x1"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xB4000000"/> </TZEN>
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</Configuration>
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<Configuration number="0x3"> <!-- Dual Bank non Secure-->
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<TZEN reference="0x0"> <ReadRegister address="0x40022070" mask="0xFF000000" value="0xC3000000"/> </TZEN>
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</Configuration>
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<Configuration number="0x5"> <!-- Empty config to avoid crash -->
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<!-- 96 KB -->
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<Configuration config="0,3">
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<Parameters address="0x20000000" name="SRAM" size="0x8000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x8000"/>
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</Field>
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</Bank>
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</Configuration>
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<Configuration config="1,2,4,5">
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<Parameters address="0x30000000" name="SRAM" size="0x8000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x30000000" name="SRAM" occurrence="0x1" size="0x8000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x08FFF80C" default="0x20000"/>
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<BootloaderVersion address="0x0BF8FFFE"/>
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<DBGMCU_CR address="0xE0042004" mask="0x06"/>
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<DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
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<RCC_APB1ENR address="0x54020C9C" mask="0x00000800"/>
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<SFSPVersion address="0x0BF860CC"/>
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<Configuration config="0,3,4,5"> <!-- dual Bank nn secure -->
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<Parameters address="0x08000000" name=" 128Kbyte Embedded Flash" size="0x20000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x8" size="0x2000"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08010000" name="sector8" occurrence="0x8" size="0x2000"/>
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</Field>
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</Bank>
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</Configuration>
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<Configuration config="1,2"> <!-- dual Bank secure -->
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<Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x20000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x10</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x0c000000" name="sector0" occurrence="0x10" size="0x2000"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x0c010000" name="sector8" occurrence="0x10" size="0x2000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Dummy config to support flash mapped at 0x0C000000 -->
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<Peripheral>
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<Name>Data EEPROM</Name> <!-- reuse EEPROM tag for Dummy config to support flash mapped at 0x0C000000 -->
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<Type>Storage</Type>
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<Description>Dummy config to support flash mapped at 0x0C000000</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<Configuration config="0,1,3,4,5">
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<Parameters address="0x0C000000" name="Flash Secure" size="0x200000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x0C000000" name="sector0" occurrence="0x80" size="0x2000"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x0C100000" name="sector128" occurrence="0x80" size="0x2000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- OTP -->
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<Peripheral>
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<Name>OTP</Name>
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<Type>Storage</Type>
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<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 2 KBytes single bank -->
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<Configuration>
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<Parameters address="0x08FFF000" name=" 2 KBytes Data OTP" size="0x800"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x2</Alignment>
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<Bank name="OTP">
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<Field>
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<Parameters address="0x08FFF000" name="OTP" occurrence="0x1" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Configuration config="0,4">
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<Bank interface="JTAG_SWD">
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<Parameters address="0x40022050" name="Bank 1" size="0x70"/>
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<Category>
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<Name>Product state</Name>
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<Field>
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<Parameters address="0x40022050" name="CUR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>PRODUCT_STATE</Name>
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<Description>Life state code.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0xED">Open</Val>
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<Val value="0x17">Provisioning</Val>
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<Val value="0x2E">Provisioned</Val>
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<Val value="0x72">Closed</Val>
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<Val value="0x5C">Locked</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="PRG" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>PRODUCT_STATE</Name>
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<Description>Life state code.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0xED">Open</Val>
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<Val value="0x17">Provisioning</Val>
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<Val value="0x2E">Provisioned</Val>
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<Val value="0x72">Closed</Val>
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<Val value="0x5C">Locked</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BORH_EN</Name>
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<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">disabled</Val>
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<Val value="0x1">enabled</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BORH_EN</Name>
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<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
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<BitOffset>0x2</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">disabled</Val>
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<Val value="0x1">enabled</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>Brownout level option status bit.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
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<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
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<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>Brownout level option status bit.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x2</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
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<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
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<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IO_VDDIO2_HSLV</Name>
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<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
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<BitOffset>0x11</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
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<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IO_VDDIO2_HSLV</Name>
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<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
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<BitOffset>0x11</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
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<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IO_VDD_HSLV</Name>
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<Description>High-speed IO at low VDD voltage status bit.</Description>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
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<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IO_VDD_HSLV</Name>
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<Description>High-speed IO at low VDD voltage status bit.</Description>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
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<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description>Standby mode freeze option status bit.</Description>
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<BitOffset>0x15</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
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<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description>Standby mode freeze option status bit.</Description>
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<BitOffset>0x15</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
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<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description>Stop mode freeze option status bit.</Description>
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<BitOffset>0x14</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
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<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description>Stop mode freeze option status bit.</Description>
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<BitOffset>0x14</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
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<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>SWAP_BANK</Name>
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<Description>Bank swapping option status bit.</Description>
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<BitOffset>0x1F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">bank 1 and bank 2 not swapped</Val>
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<Val value="0x1">bank 1 and bank 2 swapped</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>SWAP_BANK</Name>
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<Description>Bank swapping option status bit.</Description>
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<BitOffset>0x1F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Val value="0x0">bank 1 and bank 2 not swapped</Val>
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<Val value="0x1">bank 1 and bank 2 swapped</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
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<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description>IWDG control mode option status bit.</Description>
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<BitOffset>0x3</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
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<Val value="0x1">IWDG watchdog is controlled by software</Val>
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</Bit>
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</AssignedBits>
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</Field>
|
|
<Field>
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<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description>IWDG control mode option status bit.</Description>
|
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<BitOffset>0x3</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
|
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<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
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<Val value="0x1">IWDG watchdog is controlled by software</Val>
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</Bit>
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</AssignedBits>
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</Field>
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<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022070" name="Bank 2" size="0x8"/>
|
|
<Category>
|
|
<Name>User Configuration 2</Name>
|
|
<Field>
|
|
<Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022080" name="Bank 3" size="0x8"/>
|
|
<Category>
|
|
<Name>Boot Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x100" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x100" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x400220E8" name="Bank 4" size="0x8"/>
|
|
<Category>
|
|
<Name>Write sector group protection 1</Name>
|
|
<Field>
|
|
<Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x400221E8" name="Bank 5" size="0x8"/>
|
|
|
|
<Category>
|
|
<Name>Write sector group protection 2</Name>
|
|
<Field>
|
|
<Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08010000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400221EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08010000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022090" name="Bank 6" size="0x8"/>
|
|
<Category>
|
|
<Name>OTP write protection</Name>
|
|
<Field>
|
|
<Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x400220F8" name="Bank 10" size="0x8"/>
|
|
<Category>
|
|
<Name>Flash HDP bank 1</Name>
|
|
<Field>
|
|
<Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x400221F8" name="Bank 11" size="0x8"/>
|
|
<Category>
|
|
<Name>Flash HDP bank 2</Name>
|
|
<Field>
|
|
<Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Configuration>
|
|
<Configuration config="1">
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x50022050" name="Bank 1" size="0x70"/>
|
|
<Category>
|
|
<Name>Product state</Name>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="CUR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PRODUCT_STATE</Name>
|
|
<Description>Life state code.</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0xED">Open</Val>
|
|
<Val value="0x17">Provisioning</Val>
|
|
<Val value="0x2E">Provisioned</Val>
|
|
<Val value="0x72">Closed</Val>
|
|
<Val value="0x5C">Locked</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="PRG" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PRODUCT_STATE</Name>
|
|
<Description>Life state code.</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0xED">Open</Val>
|
|
<Val value="0x17">Provisioning</Val>
|
|
<Val value="0x2E">Provisioned</Val>
|
|
<Val value="0x72">Closed</Val>
|
|
<Val value="0x5C">Locked</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>BOR Level</Name>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BORH_EN</Name>
|
|
<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
|
|
<BitOffset>0x2</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">disabled</Val>
|
|
<Val value="0x1">enabled</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BORH_EN</Name>
|
|
<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
|
|
<BitOffset>0x2</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">disabled</Val>
|
|
<Val value="0x1">enabled</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>Brownout level option status bit.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
|
|
<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
|
|
<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>Brownout level option status bit.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
|
|
<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
|
|
<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDDIO2_HSLV</Name>
|
|
<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDDIO2_HSLV</Name>
|
|
<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDD_HSLV</Name>
|
|
<Description>High-speed IO at low VDD voltage status bit.</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDD_HSLV</Name>
|
|
<Description>High-speed IO at low VDD voltage status bit.</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description>Stop mode freeze option status bit.</Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description>Stop mode freeze option status bit.</Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description>Standby mode freeze option status bit.</Description>
|
|
<BitOffset>0x15</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description>Standby mode freeze option status bit.</Description>
|
|
<BitOffset>0x15</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SWAP_BANK</Name>
|
|
<Description>Bank swapping option status bit.</Description>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">bank 1 and bank 2 not swapped</Val>
|
|
<Val value="0x1">bank 1 and bank 2 swapped</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SWAP_BANK</Name>
|
|
<Description>Bank swapping option status bit.</Description>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">bank 1 and bank 2 not swapped</Val>
|
|
<Val value="0x1">bank 1 and bank 2 swapped</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description>IWDG control mode option status bit.</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">IWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description>IWDG control mode option status bit.</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">IWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x50022070" name="Bank 2" size="0x10"/>
|
|
<Category>
|
|
<Name>User Configuration 2</Name>
|
|
<Field>
|
|
<Parameters address="0x50022070" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022074" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x50022080" name="Bank 3" size="0x8"/>
|
|
<Category>
|
|
<Name>Boot Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x50022080" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x100" offset="0x0"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022084" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x100" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x500220E8" name="Bank 4" size="0x8"/>
|
|
<Category>
|
|
<Name>Write sector group protection 1</Name>
|
|
<Field>
|
|
<Parameters address="0x500220E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x500220EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x500221E8" name="Bank 5" size="0x8"/>
|
|
|
|
<Category>
|
|
<Name>Write sector group protection 2</Name>
|
|
<Field>
|
|
<Parameters address="0x500221E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x500221EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x50022090" name="Bank 6" size="0x8"/>
|
|
<Category>
|
|
<Name>OTP write protection</Name>
|
|
<Field>
|
|
<Parameters address="0x50022090" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x50022094" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x500220F8" name="Bank 10" size="0x8"/>
|
|
<Category>
|
|
<Name>Flash HDP bank 1</Name>
|
|
<Field>
|
|
<Parameters address="0x500220F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x500220FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x500221F8" name="Bank 11" size="0x8"/>
|
|
<Category>
|
|
<Name>Flash HDP bank 2</Name>
|
|
<Field>
|
|
<Parameters address="0x500221F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x500221FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Configuration>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x40022050" name="Bank 1" size="0xB0"/>
|
|
<Category>
|
|
<Name>Product state</Name>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="CUR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PRODUCT_STATE</Name>
|
|
<Description>Life state code.</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0xED">Open</Val>
|
|
<Val value="0x17">Provisioning</Val>
|
|
<Val value="0x2E">Provisioned</Val>
|
|
<Val value="0x72">Closed</Val>
|
|
<Val value="0x5C">Locked</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="PRG" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>PRODUCT_STATE</Name>
|
|
<Description>Life state code.</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0xED">Open</Val>
|
|
<Val value="0x17">Provisioning</Val>
|
|
<Val value="0x2E">Provisioned</Val>
|
|
<Val value="0x72">Closed</Val>
|
|
<Val value="0x5C">Locked</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>BOR Level</Name>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BORH_EN</Name>
|
|
<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
|
|
<BitOffset>0x2</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">disabled</Val>
|
|
<Val value="0x1">enabled</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BORH_EN</Name>
|
|
<Description>Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off</Description>
|
|
<BitOffset>0x2</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">disabled</Val>
|
|
<Val value="0x1">enabled</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>Brownout level option status bit.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
|
|
<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
|
|
<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>Brownout level option status bit.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level 1, the threshold level is low (around 2.1 V)</Val>
|
|
<Val value="0x1">BOR Level 2, the threshold level is medium (around 2.4 V)</Val>
|
|
<Val value="0x2">BOR Level 3, the threshold level is high (around 2.7 V)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDDIO2_HSLV</Name>
|
|
<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDDIO2_HSLV</Name>
|
|
<Description>High-speed IO at low VDDIO2 voltage status bit.</Description>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDD_HSLV</Name>
|
|
<Description>High-speed IO at low VDD voltage status bit.</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IO_VDD_HSLV</Name>
|
|
<Description>High-speed IO at low VDD voltage status bit.</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.7 V)</Val>
|
|
<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.7 V)</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description>Standby mode freeze option status bit.</Description>
|
|
<BitOffset>0x15</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description>Standby mode freeze option status bit.</Description>
|
|
<BitOffset>0x15</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system standby mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system standby mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description>Stop mode freeze option status bit.</Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description>Stop mode freeze option status bit.</Description>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">Independent watchdog frozen in system Stop mode</Val>
|
|
<Val value="0x1">Independent watchdog keep running in system Stop mode.</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SWAP_BANK</Name>
|
|
<Description>Bank swapping option status bit.</Description>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">bank 1 and bank 2 not swapped</Val>
|
|
<Val value="0x1">bank 1 and bank 2 swapped</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SWAP_BANK</Name>
|
|
<Description>Bank swapping option status bit.</Description>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">bank 1 and bank 2 not swapped</Val>
|
|
<Val value="0x1">bank 1 and bank 2 swapped</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description>IWDG control mode option status bit.</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">IWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description>IWDG control mode option status bit.</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">IWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">IWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description>WWDG control mode option status bit.</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">WWDG watchdog is controlled by hardware</Val>
|
|
<Val value="0x1">WWDG watchdog is controlled by software</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STOP</Name>
|
|
<Description>Core domain Stop entry reset option status bit.</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Stop mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Stop mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022054" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NRST_STDBY</Name>
|
|
<Description>Core domain Standby entry reset option status bit.</Description>
|
|
<BitOffset>0x7</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Val value="0x0">a reset is generated when entering Standby mode on core domain</Val>
|
|
<Val value="0x1">no reset generated when entering Standby mode on core domain</Val>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration 2</Name>
|
|
<Field>
|
|
<Parameters address="0x40022070" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022074" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SRAM1_ECC</Name>
|
|
<Description>ECC in SRAM1 region configuration bit</Description>
|
|
<BitOffset>0xA</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM1 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM1_RST</Name>
|
|
<Description>SRAM1 erase upon system reset</Description>
|
|
<BitOffset>0x9</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 erased when a system reset occurs</Val>
|
|
<Val value="0x1">SRAM1 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_ECC</Name>
|
|
<Description>ECC in SRAM2 region configuration bit</Description>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 ECC check enabled </Val>
|
|
<Val value="0x1">SRAM2 ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
|
|
<Bit>
|
|
<Name>BKPRAM_ECC</Name>
|
|
<Description>ECC in BKPRAM region configuration bit</Description>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">BKPRAM ECC check enabled </Val>
|
|
<Val value="0x1">BKPRAM ECC check disabled</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM2_RST</Name>
|
|
<Description>SRAM2 erase when system reset</Description>
|
|
<BitOffset>0x3</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM2 erase when system reset occurs</Val>
|
|
<Val value="0x1">SRAM2 not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Boot Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x40022080" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x100" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022084" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>NSBOOTADD</Name>
|
|
<Description>Unique Boot Entry Address</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x18</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x100" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NSBOOT_LOCK</Name>
|
|
<Description>A field locking the values of SWAP_BANK, and NSBOOTADD settings.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Values>
|
|
<Val value="0xC3">The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.</Val>
|
|
<Val value="0xB4">The NSBOOTADD and SWAP_BANK are frozen.</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>OTP write protection</Name>
|
|
<Field>
|
|
<Parameters address="0x40022090" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022094" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>LOCKBL</Name>
|
|
<Description>OTP Block Lock</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x20</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write sector group protection 1</Name>
|
|
<Field>
|
|
<Parameters address="0x400220E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400220EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn1</Name>
|
|
<Description>Bank 1 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Flash HDP bank 1</Name>
|
|
<Field>
|
|
<Parameters address="0x400220F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400220FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP1_STRT</Name>
|
|
<Description>Bank 1 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP1_END</Name>
|
|
<Description>Bank 1 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x400221E8" name="Bank 2" size="0x18"/>
|
|
<Category>
|
|
<Name>Write sector group protection 2</Name>
|
|
<Field>
|
|
<Parameters address="0x400221E8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0" offset="0x08010000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400221EC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPSGn2</Name>
|
|
<Description>Bank 2 sector group protection option status byte</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0" offset="0x08010000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Flash HDP bank 2</Name>
|
|
<Field>
|
|
<Parameters address="0x400221F8" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>R</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x400221FC" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>HDP2_STRT</Name>
|
|
<Description>Bank 2 HDP barrier start set in number of 8kb sectors</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>HDP2_END</Name>
|
|
<Description>Bank 2 HDP barrier end set in number of 8kb sectors</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>W</Access>
|
|
<Equation multiplier="0x2000" offset="0x00000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Peripheral>
|
|
</Peripherals>
|
|
</Device>
|
|
</Root> |