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495 lines
22 KiB
C
495 lines
22 KiB
C
/**
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******************************************************************************
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* @file ll_aton_platform.h
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* @author SRA Artificial Intelligence & Embedded Architectures
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* @brief Header file for defining platform dependencies
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#ifndef __LL_ATON_PLATFORM_H
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#define __LL_ATON_PLATFORM_H
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#include <stdint.h>
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#include "ll_aton_config.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Default timeout is 10s, but can be overridden */
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#ifndef ATON_EPOCH_TIMEOUT_MS
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#define ATON_EPOCH_TIMEOUT_MS 10000
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#endif
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/*** Platform dependent definitions & includes ***/
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/* Bare metal Cortex-M NCSIM simulator platform*/
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#if (LL_ATON_PLATFORM == LL_ATON_PLAT_NCSIM)
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#define ATON_PLAT_HAS_FFLUSH (0)
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#define ATON_BASE 0xA0000000
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#define SYSMEM1_BASE 0xA0080000
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#define SYSMEM2_BASE 0xA00A0000
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#define SYSMEM3_BASE 0xA00C0000
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#define SYSMEM4_BASE 0xA00E0000
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#define SYSMEM_LENGTH 0x00020000
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#define DUMMY_MEM_BASE 0x40000000
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#define DUMP_CONFIG_BASE_ADDR 0xA0108000
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#define CDMA_BASE_ADDR 0xA0100000
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#define OSPI2_BASE_ADDR 0x3D710000
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#define OSPI1_BASE_ADDR 0x3D700000
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#define OSPIIOM_BASE_ADDR 0x3D720000
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#define OSPI_HSEL_SEL 0x3D83100C
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#define OSPI1_MEM 0x60000000
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#define OSPI2_MEM 0x80000000
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#include "cm4ikmcu.h"
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/* Neuromem simulation environment */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_NEUROMEM_SIM)
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#define ATON_PLAT_HAS_FFLUSH (0)
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#define ATON_BASE 0xA0000000
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#define SYSMEM1_BASE 0xA0080000
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#define SYSMEM2_BASE 0xA00A0000
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#define SYSMEM3_BASE 0xA00C0000
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#define SYSMEM4_BASE 0xA00E0000
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#define SYSMEM_LENGTH 0x00020000
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#define DUMP_CONFIG_BASE_ADDR 0x3D807c00
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#define CDMA_BASE_ADDR 0xA0100000
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#define OSPI2_BASE_ADDR 0xA0150000
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#define OSPI1_BASE_ADDR 0xA0160000
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#define OSPI1_MEM 0x00000000
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#define OSPI2_MEM 0x80000000
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#define ATON_INT_NR (2 * 6 + 2 + 2) // 6 streng, 6 streng err, 2 convacc, 2 busif
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/* These macros are not available in Neuromem ATON.h so define them here */
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#define ATON_STRENG_INT_MASK(A, B, C) (0x003f)
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#define ATON_STRENG_ERR_INT_MASK(A, B, C) (0x0fc0)
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#define ATON_CONVACC_INT_MASK(A, B, C) (0x3000)
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#define ATON_BUSIF_INT_MASK(A, B, C) (0xc000)
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#ifndef ATON_STRENG_NUM
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#define ATON_STRENG_NUM 6
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#define ATON_CONVACC_NUM 2
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#define ATON_DECUN_NUM 1
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#define ATON_ACTIV_NUM 1
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#define ATON_ARITH_NUM 1
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#define ATON_POOL_NUM 1
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#define ATON_BUSIF_NUM 2
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#endif
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#ifndef ATON_STRENG_CTRL_DT
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#define ATON_STRENG_CTRL_DT ATON_STRENG_CTRL_RESET
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#endif
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#ifndef ATON_DECUN_CTRL_DT
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#define ATON_DECUN_CTRL_DT ATON_DECUN_CTRL_RESET
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#endif
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#ifndef ATON_CONVACC_CTRL_DT
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#define ATON_CONVACC_CTRL_DT ATON_CONVACC_CTRL_RESET
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#endif
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#ifndef ATON_ACTIV_CTRL_DT
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#define ATON_ACTIV_CTRL_DT ATON_ACTIV_CTRL_RESET
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#endif
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#ifndef ATON_ARITH_CTRL_DT
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#define ATON_ARITH_CTRL_DT ATON_ARITH_CTRL_RESET
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#endif
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#ifndef ATON_POOL_CTRL_DT
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#define ATON_POOL_CTRL_DT ATON_POOL_CTRL_RESET
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#endif
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#ifndef ATON_ACTIV_FUNC_DT
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#define ATON_ACTIV_FUNC_DT ATON_ACTIV_FUNC_RESET
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#endif
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#ifndef ATON_ACTIV_ACTIVPARAM_DT
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#define ATON_ACTIV_ACTIVPARAM_DT ATON_ACTIV_ACTIVPARAM_RESET
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#endif
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#ifndef ATON_ACTIV_ACTIVPARAM2_DT
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#define ATON_ACTIV_ACTIVPARAM2_DT ATON_ACTIV_ACTIVPARAM2_RESET
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#endif
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#include "cm4ikmcu.h"
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/* Imaging simulation environment */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_IMAGING_SIM)
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#define ATON_PLAT_HAS_FFLUSH (0)
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#define ATON_BASE 0xA0000000
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#define SYSMEM1_BASE 0xB0000000
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#define SYSMEM2_BASE 0xB0040000
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#define SYSMEM3_BASE 0xB0080000
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#define SYSMEM_LENGTH 0x00040000
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#define DUMMY_MEM_BASE 0x40000000
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#define DUMP_CONFIG_BASE_ADDR 0xA0108000
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#define CDMA_BASE_ADDR 0xA0100000
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#define OSPI2_BASE_ADDR 0x3D710000
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#define OSPI1_BASE_ADDR 0x3D700000
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#define OSPIIOM_BASE_ADDR 0x3D720000
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#define OSPI_HSEL_SEL 0x3D83100C
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#define OSPI1_MEM 0x60000000
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#define OSPI2_MEM 0x80000000
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#include "cm4ikmcu.h"
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#define ATON_STRENG_CID_CACHE_SET_ALLOC(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_CACHEABLE(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_CID(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_LINESIZE(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_PFETCH(a, b) 0
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/* Bare metal Cortex-M STICE4 FPGA platform */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STICE4)
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#define ATON_PLAT_HAS_FFLUSH (1)
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#define ATON_BASE 0x51100000
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typedef int32_t IRQn_Type;
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#include "stm32h7_map.h"
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#include <core_cm7.h>
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#define CDNN0_IRQn (123)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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/* Linux based Xilinx ZC706 FPGA platform */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_ZC706) || (LL_ATON_PLATFORM == LL_ATON_PLAT_IWAVE) || \
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(LL_ATON_PLATFORM == LL_ATON_PLAT_BITTWARE)
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#define ATON_PLAT_HAS_FFLUSH (1)
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extern uint8_t *get_zynq_aton_base(void);
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#define NVIC_EnableIRQ(x)
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#define NVIC_DisableIRQ(x)
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#define ATON_BASE (get_zynq_aton_base())
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/* Timer clock is 100MHz. Compute timeout accordingly. */
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 100 * 1000)
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/* PC based Orlando Simulator platform */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_SWEMUL)
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#define ATON_PLAT_HAS_FFLUSH (1)
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#define __WFE()
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#define NVIC_EnableIRQ(x)
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#define NVIC_DisableIRQ(x)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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/* Bare metal Cortex-M TLM simulator platform as used by MCD */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_TLM_MCD)
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#define ATON_PLAT_HAS_FFLUSH (1)
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#include "cnn1_top_mapping.h"
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#define ATON_BASE CNN1_TOP_BASEADDR
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#define SYSMEM1_BASE AXI_MEM0
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#define SYSMEM2_BASE AXI_MEM1
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#define SYSMEM3_BASE AXI_MEM2
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#define SYSMEM4_BASE AXI_MEM3
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#define SYSMEM_LENGTH 0x00020000
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#define DUMMY_MEM_BASE AXI_FLASH
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#define DUMP_CONFIG_BASE_ADDR ATON_BASE + 0x108000
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#define CDMA_BASE_ADDR ATON_BASE + 0x100000
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#define __WFE() esw_sleep()
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#define __DSB()
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#define NVIC_EnableIRQ(x)
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#define NVIC_DisableIRQ(x)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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/* PC based Test Explorer application platform */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_TSTXPL)
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#define ATON_PLAT_HAS_FFLUSH (1)
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#define __WFE() (complete_dmas())
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#define __DSB()
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#define NVIC_EnableIRQ(x)
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#define NVIC_DisableIRQ(x)
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uintptr_t get_aton_base(void);
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void complete_dmas(void);
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#define ATON_BASE (get_aton_base())
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_EC_TRACE)
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#include "ll_aton_ec_trace.h"
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#define ATON_PLAT_HAS_FFLUSH (1)
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#define ATON_BASE (get_ec_aton_base())
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#define __WFE()
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#define __DSB()
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#define NVIC_EnableIRQ(x)
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#define NVIC_DisableIRQ(x)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#define ATON_REG_WRITE_RELOC(regaddr, base, offset) \
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ec_trace_write_reloc((uintptr_t)regaddr, (uint32_t)base, (uint32_t)offset)
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#define ATON_REG_WRITE(regaddr, val) ec_trace_write((uintptr_t)regaddr, (uint32_t)val)
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#define ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, start, fsize, val) \
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ec_trace_reg_writefield(ec_trace_get_IP_id(ATON_##unitname##_BASE(id)), \
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ec_trace_get_REG_id(ATON_##unitname##_##reg##_OFFSET), start, fsize, val)
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#define ATON_REG_WRITE_FIELD(unitname, id, reg, field, val) \
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ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, ATON_##unitname##_##reg##_##field##_LSB, \
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ATON_##unitname##_##reg##_##field##_W, val)
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#define ATON_REG_POLL(unitname, id, reg, field, val) \
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ec_trace_reg_poll(ec_trace_get_IP_id(ATON_##unitname##_BASE(id)), \
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ec_trace_get_REG_id(ATON_##unitname##_##reg##_OFFSET), ATON_##unitname##_##reg##_##field##_LSB, \
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ATON_##unitname##_##reg##_##field##_W, (uint32_t)val)
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_CENTAURI)
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#define ATON_BASE 0xA0000000
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#define SYSMEM1_BASE 0xA0080000
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#define SYSMEM2_BASE 0xA00A0000
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#define SYSMEM3_BASE 0xA00C0000
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#define SYSMEM4_BASE 0xA00E0000
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#define SYSMEM_LENGTH 0x00020000
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#define DUMMY_MEM_BASE 0x40000000
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#define DUMP_CONFIG_BASE_ADDR 0xA0108000
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#define CDMA_BASE_ADDR 0xA0100000
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#define OSPI2_BASE_ADDR 0x3D710000
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#define OSPI1_BASE_ADDR 0x3D700000
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#define OSPIIOM_BASE_ADDR 0x3D720000
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#define OSPI_HSEL_SEL 0x3D83100C
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#define OSPI1_MEM 0x60000000
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#define OSPI2_MEM 0x80000000
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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//#define ATON_INT_NR (2 * 16 + 6 + 4) /* 16 streng, 6 convacc, 4 busif */
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#define ATON_INT_NR 32 //>32 not supported yet
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#if (LL_ATON_RT_MODE == LL_ATON_RT_ASYNC)
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#error Only supported `LL_ATON_RT_MODE==LL_ATON_RT_POLLING`
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#endif
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#include "cm4ikmcu.h"
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_N64)
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#define ATON_PLAT_HAS_FFLUSH (1)
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#define ATON_BASE 0x3d83d000
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#define ATON_STRENG_CID_CACHE_SET_ALLOC(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_CACHEABLE(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_CID(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_LINESIZE(a, b) 0
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#define ATON_STRENG_CID_CACHE_SET_PFETCH(a, b) 0
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STM32N6)
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// Cache maintenance
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#include "mcu_cache.h"
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#include "npu_cache.h"
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#include "stm32n6xx.h"
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#define ATON_N6_DRIVERS_v0200 \
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((0x0 << 24U) | /* MAIN */ \
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(0x2 << 16) | /* SUB1 */ \
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(0x0 << 8) | /* SUB2 */ \
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(0x0) /* RC */ \
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)
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#define ATON_GET_VERSION_RC(x) ((x)&0xFF)
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#define ATON_GET_VERSION_FIRST_THREE(x) ((x) >> 8)
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#define ATON_IS_AT_LEAST_VERSION(x, v) \
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(((ATON_GET_VERSION_RC(x) == 0x0) && (ATON_GET_VERSION_FIRST_THREE(x) >= ATON_GET_VERSION_FIRST_THREE(v))) || \
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(((ATON_GET_VERSION_RC(x) != 0x0) && (ATON_GET_VERSION_RC(v) == 0x0)) && \
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(ATON_GET_VERSION_FIRST_THREE(x) > ATON_GET_VERSION_FIRST_THREE(v))) || \
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(((ATON_GET_VERSION_RC(x) != 0x0) && (ATON_GET_VERSION_RC(v) != 0x0)) && ((x) >= (v))))
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#if !ATON_IS_AT_LEAST_VERSION(__STM32N6xx_HAL_VERSION, ATON_N6_DRIVERS_v0200)
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#define CDNN0_IRQHandler NPU_END_OF_EPOCH_IRQHandler
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#define CDNN1_IRQHandler NPU_INT1_IRQHandler
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#define CDNN2_IRQHandler NPU_INT2_IRQHandler
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#define CDNN3_IRQHandler NPU_INT3_IRQHandler
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#define CDNN0_IRQn NPU_END_OF_EPOCH_IRQn
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#define CDNN1_IRQn NPU_INT1_IRQn
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#define CDNN2_IRQn NPU_INT2_IRQn
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#define CDNN3_IRQn NPU_INT3_IRQn
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#else // ATON_IS_AT_LEAST_VERSION
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#define CDNN0_IRQHandler NPU0_IRQHandler
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#define CDNN1_IRQHandler NPU1_IRQHandler
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#define CDNN2_IRQHandler NPU2_IRQHandler
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#define CDNN3_IRQHandler NPU3_IRQHandler
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#define CDNN0_IRQn NPU0_IRQn
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#define CDNN1_IRQn NPU1_IRQn
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#define CDNN2_IRQn NPU2_IRQn
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#define CDNN3_IRQn NPU3_IRQn
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#endif // ATON_IS_AT_LEAST_VERSION
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#define ATON_PLAT_HAS_FFLUSH (0)
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#if defined(CPU_IN_SECURE_STATE)
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#define ATON_BASE NPU_BASE_S
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#else
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#define ATON_BASE NPU_BASE_NS
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#endif
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STM32H7P)
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/* Cache maintenance */
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//#include "mcu_cache.h" /* TODO */
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//#include "npu_cache.h" /* TODO */
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#include "stm32h7p4xx.h"
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#define CDNN0_IRQHandler NPU_IT0_IRQHandler
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#define CDNN1_IRQHandler NPU_IT1_IRQHandler
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#define CDNN2_IRQHandler NPU_IT2_IRQHandler
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#define CDNN3_IRQHandler NPU_IT2_IRQHandler /* Only three interrupts here */
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#define CDNN0_IRQn NPU_IT0_IRQn
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#define CDNN1_IRQn NPU_IT1_IRQn
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#define CDNN2_IRQn NPU_IT2_IRQn
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#define CDNN3_IRQn NPU_IT2_IRQn
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#define ATON_BASE 0x520E0000 /* Not yet defined in HAL */
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#define ATON_PLAT_HAS_FFLUSH (0)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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/* Stellar P3 support: TODO when information is available */
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#elif (LL_ATON_PLATFORM == LL_ATON_PLAT_STELLARP3)
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/* Cache maintenance */
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//#include "mcu_cache.h" /* TODO */
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//#include "npu_cache.h" /* TODO */
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//#include "stellarp3.h"
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#define CDNN0_IRQHandler NPU_IT0_IRQHandler
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#define CDNN1_IRQHandler NPU_IT1_IRQHandler
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#define CDNN2_IRQHandler NPU_IT2_IRQHandler
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#define CDNN3_IRQHandler NPU_IT3_IRQHandler
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#define CDNN0_IRQn 506 /* To R52 Kite Cluster */
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#define CDNN1_IRQn 507 /* To R52 Kite Cluster */
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#define CDNN2_IRQn 92 /* To Cortex-M4 */
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#define CDNN3_IRQn 93 /* To Cortex-M4 */
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#define ATON_BASE 0x75600000
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#define ATON_PLAT_HAS_FFLUSH (0)
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#define ATON_EPOCH_TIMEOUT (ATON_EPOCH_TIMEOUT_MS * 1000)
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#else
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#error No target platform is specified. Please define macro `LL_ATON_PLATFORM`
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#endif
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// may be included just here because of the platform dependent definitions (above all `ATON_BASE`)
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#include "ATON.h"
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#include "ll_aton_rcompat.h"
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/* Default macro for physical to virtual address translation (direct mapping) */
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#ifndef ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR
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#define ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR(address) (address)
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#endif // !ATON_LIB_PHYSICAL_TO_VIRTUAL_ADDR
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/* Default macro for virtual to physical address translation (direct mapping) */
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#ifndef ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR
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#define ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR(address) (address)
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#endif // !ATON_LIB_VIRTUAL_TO_PHYSICAL_ADDR
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// converts signed shift (negative value are left shift) to HW encoding Range 39:0. No shift 16
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#ifndef ATON_SHIFT
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#define ATON_SHIFT(x) ((x) + 16)
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#endif // ATON_SHIFT
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// Generic boilerplate for enabling an ATON unit
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#define ATON_ENABLE(unitname, id) ATON_REG_WRITE_FIELD(unitname, id, CTRL, EN, 1)
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// Generic boilerplate for disabling, stopping pending transactions (aka "clearing"), and clearing the configuration of
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// an ATON unit
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#ifndef ATON_DISABLE_CLR_CONFCLR
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#define ATON_DISABLE_CLR_CONFCLR(unitname, id) \
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do \
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{ \
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t = ATON_##unitname##_CTRL_DT; \
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t = ATON_##unitname##_CTRL_SET_EN(t, 0); \
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t = ATON_##unitname##_CTRL_SET_CLR(t, 1); \
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ATON_##unitname##_CTRL_SET(id, t); \
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/* wait for unit to terminate clearing of configuration registers */ \
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ATON_REG_POLL(unitname, id, CTRL, CLR, 0); \
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\
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t = ATON_##unitname##_CTRL_DT; \
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t = ATON_##unitname##_CTRL_SET_CONFCLR(t, 1); \
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ATON_##unitname##_CTRL_SET(id, t); \
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/* wait for unit to terminate clearing of configuration registers */ \
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ATON_REG_POLL(unitname, id, CTRL, CONFCLR, 0); \
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} while (0)
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#endif // ATON_DISABLE_CLR_CONFCLR
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#ifndef ATON_REG_WRITE_RELOC
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#define ATON_REG_WRITE_RELOC(regaddr, base, offset) \
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do \
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{ \
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*(volatile uint32_t *)(uintptr_t)(regaddr) = (base) + (offset); \
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} while (0)
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#endif // ATON_REG_WRITE_RELOC
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#ifndef ATON_REG_WRITE
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#define ATON_REG_WRITE(regaddr, val) \
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do \
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{ \
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*(volatile uint32_t *)(uintptr_t)(regaddr) = (val); \
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} while (0)
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#endif // ATON_REG_WRITE
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#ifndef ATON_REG_WRITE_FIELD_RANGE
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#define ATON_REG_WRITE_FIELD_RANGE(unitname, id, reg, start, fsize, val) \
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do \
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{ \
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uint32_t t = ATON_##unitname##_##reg##_GET(id); \
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t = ATON_SET_FIELD(t, start, fsize, val); \
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ATON_##unitname##_##reg##_SET(id, t); \
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} while (0)
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#endif // ATON_REG_WRITE_FIELD_RANGE
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#ifndef ATON_REG_WRITE_FIELD
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#define ATON_REG_WRITE_FIELD(unitname, id, reg, field, val) \
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do \
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{ \
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uint32_t t = ATON_##unitname##_##reg##_GET(id); \
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t = ATON_##unitname##_##reg##_SET_##field(t, val); \
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ATON_##unitname##_##reg##_SET(id, t); \
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} while (0)
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#endif // ATON_REG_WRITE_FIELD
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#ifndef ATON_REG_POLL
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#define ATON_REG_POLL(unitname, id, reg, field, val) \
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do \
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{ \
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while (ATON_##unitname##_##reg##_GET_##field(ATON_##unitname##_##reg##_GET(id)) != val) \
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{ \
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} \
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} while (0)
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#endif // ATON_REG_POLL
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/* Interrupt line(s) to use */
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/* ATON_STD_IRQ_LINE MUST be within the range of available ATON interrupt lines, i.e. within [0 - 3] */
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#ifndef ATON_STD_IRQ_LINE
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#define ATON_STD_IRQ_LINE 0
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#endif
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#if (ATON_STD_IRQ_LINE != 0) && (ATON_STD_IRQ_LINE != 1) && (ATON_STD_IRQ_LINE != 2) && (ATON_STD_IRQ_LINE != 3)
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#error invalid interrupt line number `ATON_STD_IRQ_LINE` (must be in range [0 - 3])
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#endif // ATON_STD_IRQ_LINE
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// Beyond macros may be defined just here
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#define ATON_STD_IRQHandler LL_ATON_CONCAT3(CDNN, ATON_STD_IRQ_LINE, _IRQHandler)
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#define ATON_STD_IRQn LL_ATON_CONCAT3(CDNN, ATON_STD_IRQ_LINE, _IRQn)
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#define ATON_STD_INTANDMSK LL_ATON_CONCAT(INTANDMSK, ATON_STD_IRQ_LINE)
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#define ATON_STD_INTORMSK LL_ATON_CONCAT(INTORMSK, ATON_STD_IRQ_LINE)
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#define ATON_INTCTRL_STD_INTANDMSK_SET(DATA) ATON_INTCTRL_INTANDMSK_SET(0, ATON_STD_IRQ_LINE, DATA)
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#define ATON_INTCTRL_STD_INTANDMSK_GET ATON_INTCTRL_INTANDMSK_GET(0, ATON_STD_IRQ_LINE)
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#define ATON_INTCTRL_STD_INTORMSK_SET(DATA) ATON_INTCTRL_INTORMSK_SET(0, ATON_STD_IRQ_LINE, DATA)
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#define ATON_INTCTRL_STD_INTORMSK_GET ATON_INTCTRL_INTORMSK_GET(0, ATON_STD_IRQ_LINE)
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#if (ATON_INT_NR > 32)
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#define ATON_INTCTRL_STD_INTORMSK_H_SET(DATA) ATON_INTCTRL_INTORMSK_H_SET(0, ATON_STD_IRQ_LINE, DATA)
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#define ATON_INTCTRL_STD_INTANDMSK_H_SET(DATA) ATON_INTCTRL_INTANDMSK_H_SET(0, ATON_STD_IRQ_LINE, DATA)
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#endif // (ATON_INT_NR > 32)
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#ifdef __cplusplus
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}
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#endif
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#endif // __LL_ATON_PLATFORM_H
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