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507 lines
17 KiB
C
507 lines
17 KiB
C
/*
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* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <nrfx.h>
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#if NRFX_CHECK(NRFX_PWM_ENABLED)
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#if !(NRFX_CHECK(NRFX_PWM0_ENABLED) || NRFX_CHECK(NRFX_PWM1_ENABLED) || \
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NRFX_CHECK(NRFX_PWM2_ENABLED) || NRFX_CHECK(NRFX_PWM3_ENABLED))
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#error "No enabled PWM instances. Check <nrfx_config.h>."
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#endif
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#include <nrfx_pwm.h>
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#include <hal/nrf_gpio.h>
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#define NRFX_LOG_MODULE PWM
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#include <nrfx_log.h>
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#if NRFX_CHECK(NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
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// The workaround uses interrupts to wake up the CPU and ensure it is active
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// when PWM is about to start a DMA transfer. For initial transfer, done when
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// a playback is started via PPI, a specific EGU instance is used to generate
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// an interrupt. During the playback, the PWM interrupt triggered on SEQEND
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// event of a preceding sequence is used to protect the transfer done for
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// the next sequence to be played.
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#include <hal/nrf_egu.h>
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#define USE_DMA_ISSUE_WORKAROUND
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#endif
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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#define EGU_IRQn(i) EGU_IRQn_(i)
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#define EGU_IRQn_(i) SWI##i##_EGU##i##_IRQn
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#define EGU_IRQHandler(i) EGU_IRQHandler_(i)
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#define EGU_IRQHandler_(i) nrfx_egu_##i##_irq_handler
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#define DMA_ISSUE_EGU_IDX NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE
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#define DMA_ISSUE_EGU NRFX_CONCAT_2(NRF_EGU, DMA_ISSUE_EGU_IDX)
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#define DMA_ISSUE_EGU_IRQn EGU_IRQn(DMA_ISSUE_EGU_IDX)
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#define DMA_ISSUE_EGU_IRQHandler EGU_IRQHandler(DMA_ISSUE_EGU_IDX)
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#endif
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// Control block - driver instance local data.
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typedef struct
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{
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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uint32_t starting_task_address;
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#endif
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nrfx_pwm_handler_t handler;
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void * p_context;
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nrfx_drv_state_t volatile state;
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uint8_t flags;
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} pwm_control_block_t;
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static pwm_control_block_t m_cb[NRFX_PWM_ENABLED_COUNT];
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static void configure_pins(nrfx_pwm_t const * p_instance,
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nrfx_pwm_config_t const * p_config)
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{
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uint32_t out_pins[NRF_PWM_CHANNEL_COUNT];
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uint8_t i;
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for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
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{
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uint8_t output_pin = p_config->output_pins[i];
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if (output_pin != NRFX_PWM_PIN_NOT_USED)
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{
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bool inverted = output_pin & NRFX_PWM_PIN_INVERTED;
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out_pins[i] = output_pin & ~NRFX_PWM_PIN_INVERTED;
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if (inverted)
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{
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nrf_gpio_pin_set(out_pins[i]);
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}
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else
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{
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nrf_gpio_pin_clear(out_pins[i]);
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}
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nrf_gpio_cfg_output(out_pins[i]);
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}
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else
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{
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out_pins[i] = NRF_PWM_PIN_NOT_CONNECTED;
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}
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}
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nrf_pwm_pins_set(p_instance->p_registers, out_pins);
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}
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nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * p_instance,
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nrfx_pwm_config_t const * p_config,
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nrfx_pwm_handler_t handler,
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void * p_context)
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{
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NRFX_ASSERT(p_config);
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nrfx_err_t err_code;
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pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
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{
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err_code = NRFX_ERROR_INVALID_STATE;
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NRFX_LOG_WARNING("Function: %s, error code: %s.",
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__func__,
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NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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p_cb->handler = handler;
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p_cb->p_context = p_context;
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configure_pins(p_instance, p_config);
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nrf_pwm_enable(p_instance->p_registers);
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nrf_pwm_configure(p_instance->p_registers,
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p_config->base_clock, p_config->count_mode, p_config->top_value);
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nrf_pwm_decoder_set(p_instance->p_registers,
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p_config->load_mode, p_config->step_mode);
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nrf_pwm_shorts_set(p_instance->p_registers, 0);
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nrf_pwm_int_set(p_instance->p_registers, 0);
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nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_LOOPSDONE);
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nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND0);
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nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND1);
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nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
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// The workaround for nRF52 Anomaly 109 "protects" DMA transfers by handling
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// interrupts generated on SEQEND0 and SEQEND1 events (this ensures that
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// the 64 MHz clock is ready when data for the next sequence to be played
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// is read). Therefore, the PWM interrupt must be enabled even if the event
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// handler is not used.
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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NRFX_IRQ_PRIORITY_SET(DMA_ISSUE_EGU_IRQn, p_config->irq_priority);
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NRFX_IRQ_ENABLE(DMA_ISSUE_EGU_IRQn);
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#else
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if (p_cb->handler)
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#endif
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{
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NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_registers),
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p_config->irq_priority);
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NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_registers));
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}
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p_cb->state = NRFX_DRV_STATE_INITIALIZED;
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err_code = NRFX_SUCCESS;
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NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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void nrfx_pwm_uninit(nrfx_pwm_t const * p_instance)
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{
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pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_registers));
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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NRFX_IRQ_DISABLE(DMA_ISSUE_EGU_IRQn);
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#endif
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nrf_pwm_disable(p_instance->p_registers);
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p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
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}
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static uint32_t start_playback(nrfx_pwm_t const * p_instance,
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pwm_control_block_t * p_cb,
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uint8_t flags,
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nrf_pwm_task_t starting_task)
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{
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p_cb->state = NRFX_DRV_STATE_POWERED_ON;
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p_cb->flags = flags;
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if (p_cb->handler)
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{
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// The notification about finished playback is by default enabled,
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// but this can be suppressed.
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// The notification that the peripheral has stopped is always enabled.
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uint32_t int_mask = NRF_PWM_INT_LOOPSDONE_MASK |
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NRF_PWM_INT_STOPPED_MASK;
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// The workaround for nRF52 Anomaly 109 "protects" DMA transfers by
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// handling interrupts generated on SEQEND0 and SEQEND1 events (see
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// 'nrfx_pwm_init'), hence these events must be always enabled
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// to generate interrupts.
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// However, the user handler is called for them only when requested
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// (see 'irq_handler').
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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int_mask |= NRF_PWM_INT_SEQEND0_MASK | NRF_PWM_INT_SEQEND1_MASK;
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#else
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if (flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ0)
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{
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int_mask |= NRF_PWM_INT_SEQEND0_MASK;
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}
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if (flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ1)
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{
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int_mask |= NRF_PWM_INT_SEQEND1_MASK;
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}
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#endif
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if (flags & NRFX_PWM_FLAG_NO_EVT_FINISHED)
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{
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int_mask &= ~NRF_PWM_INT_LOOPSDONE_MASK;
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}
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nrf_pwm_int_set(p_instance->p_registers, int_mask);
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}
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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else
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{
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nrf_pwm_int_set(p_instance->p_registers,
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NRF_PWM_INT_SEQEND0_MASK | NRF_PWM_INT_SEQEND1_MASK);
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}
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#endif
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nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
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if (flags & NRFX_PWM_FLAG_START_VIA_TASK)
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{
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uint32_t starting_task_address =
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nrf_pwm_task_address_get(p_instance->p_registers, starting_task);
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#if defined(USE_DMA_ISSUE_WORKAROUND)
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// To "protect" the initial DMA transfer it is required to start
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// the PWM by triggering the proper task from EGU interrupt handler,
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// it is not safe to do it directly via PPI.
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p_cb->starting_task_address = starting_task_address;
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nrf_egu_int_enable(DMA_ISSUE_EGU, nrf_egu_channel_int_get(p_instance->drv_inst_idx));
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return nrf_egu_task_address_get(DMA_ISSUE_EGU,
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nrf_egu_trigger_task_get(p_instance->drv_inst_idx));
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#else
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return starting_task_address;
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#endif
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}
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nrf_pwm_task_trigger(p_instance->p_registers, starting_task);
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return 0;
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}
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uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * p_instance,
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nrf_pwm_sequence_t const * p_sequence,
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uint16_t playback_count,
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uint32_t flags)
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{
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pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_ASSERT(playback_count > 0);
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NRFX_ASSERT(nrfx_is_in_ram(p_sequence->values.p_raw));
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// To take advantage of the looping mechanism, we need to use both sequences
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// (single sequence can be played back only once).
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nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence);
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nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence);
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bool odd = (playback_count & 1);
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nrf_pwm_loop_set(p_instance->p_registers,
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(playback_count / 2) + (odd ? 1 : 0));
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uint32_t shorts_mask;
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if (flags & NRFX_PWM_FLAG_STOP)
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{
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shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
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}
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else if (flags & NRFX_PWM_FLAG_LOOP)
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{
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shorts_mask = odd ? NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK
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: NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
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}
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else
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{
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shorts_mask = 0;
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}
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nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
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NRFX_LOG_INFO("Function: %s, sequence length: %d.",
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__func__,
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p_sequence->length);
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NRFX_LOG_DEBUG("Sequence data:");
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NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence->values.p_raw,
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p_sequence->length * sizeof(uint16_t));
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return start_playback(p_instance, p_cb, flags,
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odd ? NRF_PWM_TASK_SEQSTART1 : NRF_PWM_TASK_SEQSTART0);
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}
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uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * p_instance,
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nrf_pwm_sequence_t const * p_sequence_0,
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nrf_pwm_sequence_t const * p_sequence_1,
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uint16_t playback_count,
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uint32_t flags)
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{
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pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_ASSERT(playback_count > 0);
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NRFX_ASSERT(nrfx_is_in_ram(p_sequence_0->values.p_raw));
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NRFX_ASSERT(nrfx_is_in_ram(p_sequence_1->values.p_raw));
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nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence_0);
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nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence_1);
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nrf_pwm_loop_set(p_instance->p_registers, playback_count);
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uint32_t shorts_mask;
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if (flags & NRFX_PWM_FLAG_STOP)
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{
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shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
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}
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else if (flags & NRFX_PWM_FLAG_LOOP)
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{
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shorts_mask = NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
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}
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else
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{
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shorts_mask = 0;
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}
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nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
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NRFX_LOG_INFO("Function: %s, sequence 0 length: %d.",
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__func__,
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p_sequence_0->length);
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NRFX_LOG_INFO("Function: %s, sequence 1 length: %d.",
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__func__,
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p_sequence_1->length);
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NRFX_LOG_DEBUG("Sequence 0 data:");
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NRFX_LOG_HEXDUMP_DEBUG(p_sequence_0->values.p_raw,
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p_sequence_0->length * sizeof(uint16_t));
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NRFX_LOG_DEBUG("Sequence 1 data:");
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NRFX_LOG_HEXDUMP_DEBUG(p_sequence_1->values.p_raw,
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p_sequence_1->length * sizeof(uint16_t));
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return start_playback(p_instance, p_cb, flags, NRF_PWM_TASK_SEQSTART0);
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}
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bool nrfx_pwm_stop(nrfx_pwm_t const * p_instance,
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bool wait_until_stopped)
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{
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NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state != NRFX_DRV_STATE_UNINITIALIZED);
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bool ret_val = false;
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if (nrfx_pwm_is_stopped(p_instance))
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{
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ret_val = true;
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}
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else
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{
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nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP);
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do {
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if (nrfx_pwm_is_stopped(p_instance))
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{
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ret_val = true;
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break;
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}
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} while (wait_until_stopped);
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}
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NRFX_LOG_INFO("%s returned %d.", __func__, ret_val);
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return ret_val;
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}
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bool nrfx_pwm_is_stopped(nrfx_pwm_t const * p_instance)
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{
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pwm_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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bool ret_val = false;
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// If the event handler is used (interrupts are enabled), the state will
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// be changed in interrupt handler when the STOPPED event occurs.
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if (p_cb->state != NRFX_DRV_STATE_POWERED_ON)
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{
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ret_val = true;
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}
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// If interrupts are disabled, we must check the STOPPED event here.
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if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED))
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{
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p_cb->state = NRFX_DRV_STATE_INITIALIZED;
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NRFX_LOG_INFO("Disabled.");
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ret_val = true;
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}
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NRFX_LOG_INFO("%s returned %d.", __func__, ret_val);
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return ret_val;
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}
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static void irq_handler(NRF_PWM_Type * p_pwm, pwm_control_block_t * p_cb)
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{
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// The user handler is called for SEQEND0 and SEQEND1 events only when the
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// user asks for it (by setting proper flags when starting the playback).
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if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND0))
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{
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nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND0);
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if ((p_cb->flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ0) && p_cb->handler)
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{
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p_cb->handler(NRFX_PWM_EVT_END_SEQ0, p_cb->p_context);
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}
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}
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if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND1))
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{
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nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND1);
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if ((p_cb->flags & NRFX_PWM_FLAG_SIGNAL_END_SEQ1) && p_cb->handler)
|
|
{
|
|
p_cb->handler(NRFX_PWM_EVT_END_SEQ1, p_cb->p_context);
|
|
}
|
|
}
|
|
// For LOOPSDONE the handler is called by default, but the user can disable
|
|
// this (via flags).
|
|
if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_LOOPSDONE))
|
|
{
|
|
nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_LOOPSDONE);
|
|
if (!(p_cb->flags & NRFX_PWM_FLAG_NO_EVT_FINISHED) && p_cb->handler)
|
|
{
|
|
p_cb->handler(NRFX_PWM_EVT_FINISHED, p_cb->p_context);
|
|
}
|
|
}
|
|
|
|
// The STOPPED event is always propagated to the user handler.
|
|
if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_STOPPED))
|
|
{
|
|
nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_STOPPED);
|
|
|
|
p_cb->state = NRFX_DRV_STATE_INITIALIZED;
|
|
if (p_cb->handler)
|
|
{
|
|
p_cb->handler(NRFX_PWM_EVT_STOPPED, p_cb->p_context);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
#if defined(USE_DMA_ISSUE_WORKAROUND)
|
|
// See 'start_playback' why this is needed.
|
|
void DMA_ISSUE_EGU_IRQHandler(void)
|
|
{
|
|
for (uint8_t i = 0; i < NRFX_PWM_ENABLED_COUNT; i++)
|
|
{
|
|
nrf_egu_event_t event = nrf_egu_triggered_event_get(i);
|
|
if (nrf_egu_event_check(DMA_ISSUE_EGU, event))
|
|
{
|
|
nrf_egu_event_clear(DMA_ISSUE_EGU, event);
|
|
*(volatile uint32_t *)(m_cb[i].starting_task_address) = 1;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
#if NRFX_CHECK(NRFX_PWM0_ENABLED)
|
|
void nrfx_pwm_0_irq_handler(void)
|
|
{
|
|
irq_handler(NRF_PWM0, &m_cb[NRFX_PWM0_INST_IDX]);
|
|
}
|
|
#endif
|
|
|
|
#if NRFX_CHECK(NRFX_PWM1_ENABLED)
|
|
void nrfx_pwm_1_irq_handler(void)
|
|
{
|
|
irq_handler(NRF_PWM1, &m_cb[NRFX_PWM1_INST_IDX]);
|
|
}
|
|
#endif
|
|
|
|
#if NRFX_CHECK(NRFX_PWM2_ENABLED)
|
|
void nrfx_pwm_2_irq_handler(void)
|
|
{
|
|
irq_handler(NRF_PWM2, &m_cb[NRFX_PWM2_INST_IDX]);
|
|
}
|
|
#endif
|
|
|
|
#if NRFX_CHECK(NRFX_PWM3_ENABLED)
|
|
void nrfx_pwm_3_irq_handler(void)
|
|
{
|
|
irq_handler(NRF_PWM3, &m_cb[NRFX_PWM3_INST_IDX]);
|
|
}
|
|
#endif
|
|
|
|
#endif // NRFX_CHECK(NRFX_PWM_ENABLED)
|