smartknob/electronics/scripts/export_jlcpcb.py
Scott Bezek 56feeb484c
Fab automation (#2)
- Use KiKit for fab automation
- Add splitflap scripts for exporting pcb pdfs, and switch to splitflap script for 3d rendering (for consistency with fab automation)
- Added support in 3d rendering scripts for soldermask & silkscreen colors, option to skip virtual components
- Added silkscreen to base and screen pcbs for commit and date info
2022-02-15 01:27:38 -08:00

71 lines
2.1 KiB
Python
Executable File

#!/usr/bin/env python3
# Copyright 2021 Scott Bezek and the splitflap contributors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import argparse
import logging
import os
import subprocess
import sys
electronics_root = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
repo_root = os.path.dirname(electronics_root)
sys.path.append(repo_root)
from util import file_util
from export_util import (
versioned_file,
)
logging.basicConfig(level=logging.DEBUG)
logger = logging.getLogger(__name__)
def export_jlcpcb(pcb, schematic, alt_fields):
pcb_file = os.path.abspath(pcb)
output_dir = os.path.join(electronics_root, 'build', os.path.splitext(os.path.basename(pcb_file))[0] + '-jlc')
file_util.mkdir_p(output_dir)
with versioned_file(pcb_file):
command = [
'kikit',
'fab',
'jlcpcb',
]
if schematic is not None:
schematic_file = os.path.abspath(schematic)
command += [
'--assembly',
'--schematic',
schematic_file,
'--field',
]
command.append(','.join(alt_fields + ['LCSC']))
command += [
pcb_file,
output_dir,
]
subprocess.check_call(command)
if __name__ == '__main__':
parser = argparse.ArgumentParser()
parser.add_argument('pcb')
parser.add_argument('--assembly-schematic')
parser.add_argument('--alt-fields', nargs='+')
args = parser.parse_args()
export_jlcpcb(args.pcb, args.assembly_schematic, args.alt_fields)