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ports/alif: fix using I3C interface in I2C mode
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310eeae048
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110a93695f
@ -173,6 +173,10 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
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while (inst->I3C_RESET_CTRL & 0x1) {
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}
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i3c_master_set_dynamic_addr(inst);
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i3c_master_enable_interrupts(inst);
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// Initialize I2C controller
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i3c_master_init(inst);
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@ -401,6 +405,14 @@ static int omv_i3c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32
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I3C_Type *base = i2c->inst;
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i3c_add_slv_to_dat(base, I2C_DAT_INDEX, 0, xfer->address);
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i3c_xfer.xfer_cmd.speed = I3C_SPEED_SDR0;
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// i3c_xfer.addr = xfer->address;
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i3c_xfer.xfer_cmd.addr_index = I2C_DAT_INDEX;
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// i3c_xfer.xfer_cmd.addr_depth = 1U;
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i3c_xfer.xfer_cmd.data_len = xfer->size;
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if (xfer->direction == I2C_TRANSFER_READ) {
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i3c_xfer.rx_buf = xfer->data;
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i3c_xfer.rx_len = xfer->size;
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@ -414,7 +426,7 @@ static int omv_i3c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32
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// Wait for the transfer to finish.
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mp_uint_t tick_start = mp_hal_ticks_ms();
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/* Waits till some response received */
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while (!(base->I3C_QUEUE_STATUS_LEVEL & I3C_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_Msk)) {
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while (base->I3C_INTR_STATUS == 0) {
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if ((mp_hal_ticks_ms() - tick_start) >= timeout) {
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// Should not raise exception as we're not always in nlr context.
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ret = -1;
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@ -423,11 +435,11 @@ static int omv_i3c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32
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mp_event_handle_nowait();
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}
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uint32_t status = base->I3C_INTR_STATUS;
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// See Table 15-81 Response Data Structure
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uint32_t resp = base->I3C_RESPONSE_QUEUE_PORT;
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if ((I3C_RESPONSE_QUEUE_PORT_ERR_STATUS(resp)) ||
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(I3C_RESPONSE_QUEUE_PORT_TID(resp) != i3c_xfer.xfer_cmd.port_id)) {
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if ((status & I3C_INTR_STATUS_TRANSFER_ERR_STS) || I3C_RESPONSE_QUEUE_PORT_ERR_STATUS(resp)) {
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ret = -1;
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goto cleanup;
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}
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@ -138,14 +138,28 @@ int omv_i3c_init(omv_i2c_t *i3c, uint32_t bus_id, uint32_t speed) {
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while (base->I3C_RESET_CTRL & 0x1) {
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}
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i3c_master_set_dynamic_addr(base);
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i3c_master_enable_interrupts(base);
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/* Sets Slave Interrupt Request acceptability at master side */
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i3c_master_setup_slv_intr_req_ctrl(base, false);
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/* Sets Master Request acceptability at master side */
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i3c_master_setup_mst_req_ctrl(base, false);
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/* Sets up HJ acceptability at master side */
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i3c_master_setup_hot_join_ctrl(base, false);
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// Initialize I2C controller
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i3c_master_init(base);
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// Initialize I3C controller
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i3c_master_init(base);
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// Configure clock and speed.
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i3c_normal_bus_clk_cfg(base, speed);
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i3c_master_set_dynamic_addr(base);
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i3c->initialized = true;
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return 0;
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}
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