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543 lines
17 KiB
C
543 lines
17 KiB
C
/*
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* Copyright (C) 2023-2024 OpenMV, LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Any redistribution, use, or modification in source or binary form
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* is done solely for personal benefit and not for any commercial
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* purpose or for monetary gain. For commercial licensing options,
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* please contact openmv@openmv.io
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*
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* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
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* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Alif I3C driver.
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include <string.h>
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#include "py/mphal.h"
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#include "py/runtime.h"
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#include "omv_portconfig.h"
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#include "omv_boardconfig.h"
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#include "alif_hal.h"
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#include "omv_gpio.h"
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#include "omv_common.h"
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#include "omv_i3c.h"
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#include "sys_ctrl_i3c.h"
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#define I3C_SCAN_TIMEOUT (10)
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#define I3C_XFER_TIMEOUT (1000)
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/* I3C CCC (Common Command Codes) related definitions */
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#define I3C_CCC_DIRECT BIT(7)
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#define I3C_CCC_ID(id, broadcast) ((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
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/* Commands valid in both broadcast and unicast modes */
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#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
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#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
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#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
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#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
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#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
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#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
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#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
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#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
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/* Broadcast-only commands */
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#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
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#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
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#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
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#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
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#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true)
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/* Unicast-only commands */
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#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
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#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
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#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
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#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
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#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
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#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
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#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
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#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
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#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
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#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
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#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
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#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
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#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
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/* List of some Defining byte values */
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#define I3C_CCC_DEF_BYTE_SYNC_TICK 0x7F
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#define I3C_CCC_DEF_BYTE_DELAY_TIME 0xBF
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#define I3C_CCC_DEF_BYTE_ASYNC_MODE0 0xDF
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#define I3C_CCC_DEF_BYTE_ASYNC_MODE1 0xEF
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#define I3C_CCC_DEF_BYTE_ASYNC_MODE2 0xF7
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#define I3C_CCC_DEF_BYTE_ASYNC_MODE3 0xFB
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#define I3C_CCC_DEF_BYTE_ASYNC_TRIG 0xFD
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#define I3C_CCC_DEF_BYTE_TPH 0x3F
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#define I3C_CCC_DEF_BYTE_TU 0x9F
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#define I3C_CCC_DEF_BYTE_ODR 0x8F
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int omv_i3c_init(omv_i2c_t *i3c, uint32_t bus_id, uint32_t speed) {
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i3c->id = bus_id;
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i3c->initialized = false;
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i3c->cw_size = 0;
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i3c->speed = speed;
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switch (speed) {
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case OMV_I3C_SPEED_SDR:
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speed = I3C_BUS_SDR0_SCL_RATE; // 12.5 Mbit/s
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break;
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case OMV_I3C_SPEED_HDR:
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speed = I3C_BUS_MAX_I3C_SCL_RATE; // 12.9 kbit/s
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break;
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default:
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return -1;
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}
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switch (bus_id) {
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#if defined(OMV_I3C0_ID)
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case OMV_I3C0_ID: {
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i3c->inst = (I3C_Type *) I3C_BASE;
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i3c->scl_pin = OMV_I3C0_SCL_PIN;
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i3c->sda_pin = OMV_I3C0_SDA_PIN;
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break;
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}
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#endif
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default:
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return -1;
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}
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alif_hal_i3c_init(bus_id);
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// I3C controller in non-legacy mode.
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I3C_Type *base = i3c->inst;
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// Core soft-reset.
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base->I3C_RESET_CTRL = 0x1;
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while (base->I3C_RESET_CTRL & 0x1) {
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}
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i3c_master_set_dynamic_addr(base);
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i3c_master_enable_interrupts(base);
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/* Sets Slave Interrupt Request acceptability at master side */
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i3c_master_setup_slv_intr_req_ctrl(base, false);
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/* Sets Master Request acceptability at master side */
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i3c_master_setup_mst_req_ctrl(base, false);
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/* Sets up HJ acceptability at master side */
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i3c_master_setup_hot_join_ctrl(base, false);
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// Initialize I2C controller
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i3c_master_init(base);
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// Initialize I3C controller
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i3c_master_init(base);
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// Configure clock and speed.
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i3c_normal_bus_clk_cfg(base, speed);
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i3c->initialized = true;
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return 0;
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}
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int omv_i3c_deinit(omv_i2c_t *i3c) {
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if (i3c->initialized) {
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// TODO
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i3c->initialized = false;
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}
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return 0;
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}
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static int omv_i3c_get_addr_pos(omv_i2c_t *i3c, uint8_t addr) {
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size_t pos;
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for (pos = 0; pos < i3c->cw_size; pos++) {
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if (addr == i3c->cw_buf[pos]) {
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return (int) pos;
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}
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}
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return -1;
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}
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static void omv_i3c_add_dyn_addr_parity(uint8_t *dyn_addr) {
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uint8_t bit_iter = 0U;
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uint8_t xor_value = 0U;
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/* XOR the 1st 7 bits of dynamic address*/
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xor_value = ((*dyn_addr) & (1U << 0U));
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for (bit_iter = 1U; bit_iter < 7U; bit_iter++) {
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xor_value ^= (((*dyn_addr) >> bit_iter) & 1U);
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}
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/* Assign the negated XOR value to 7th
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* bit of dynamic address */
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*dyn_addr |= ((~xor_value) << 7U);
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}
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static int32_t omv_i3c_gen_dyn_addr(omv_i2c_t *i3c, uint8_t *ref_dyn_addr) {
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if (i3c->cw_size >= I3C_MAX_DEVS) {
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return -1;
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}
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/* we start assigning addresses from 0x09 */
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*ref_dyn_addr = (uint8_t) i3c->cw_size + I3C_NEXT_SLAVE_ADDR_OFFSET;
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while (true) {
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/* Checks if new address is not a self address and
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* not already assigned to some slave. If true then,
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* assign it otherwise increment it */
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if ((omv_i3c_get_addr_pos(i3c, *ref_dyn_addr) < 0) && (i3c_get_dynamic_addr(i3c->inst) != *ref_dyn_addr)) {
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break;
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}
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(*ref_dyn_addr)++;
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}
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i3c->cw_buf[i3c->cw_size] = *ref_dyn_addr;
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// i3c->cw_buf[i3c->cw_size] &= (~I3C_TARGET_SLAVE_TYPE_I2C);
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return (int32_t) i3c->cw_size++;
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}
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static int omv_i3c_transfer_wait(I3C_Type *base, i3c_xfer_t *xfer, uint32_t timeout) {
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// Wait for the transfer to finish.
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mp_uint_t tick_start = mp_hal_ticks_ms();
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/* Waits till some response received */
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while (!(base->I3C_QUEUE_STATUS_LEVEL & I3C_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_Msk)) {
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if ((mp_hal_ticks_ms() - tick_start) >= timeout) {
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// Should not raise exception as we're not always in nlr context.
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return -1;
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}
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mp_event_handle_nowait();
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}
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// See Table 15-81 Response Data Structure
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uint32_t resp = base->I3C_RESPONSE_QUEUE_PORT;
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if ((I3C_RESPONSE_QUEUE_PORT_ERR_STATUS(resp)) ||
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(I3C_RESPONSE_QUEUE_PORT_TID(resp) != xfer->xfer_cmd.port_id)) {
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return -1;
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}
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return 0;
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}
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static void omv_i3c_transfer_end(I3C_Type *base) {
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i3c_clear_xfer_error(base);
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i3c_resume(base);
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}
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static int omv_i3c_send_command_assign(I3C_Type *base, uint8_t cmd_id, uint8_t addr_index, uint8_t addr_depth) {
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i3c_xfer_t xfer = {0};
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xfer.xfer_cmd.cmd_id = cmd_id;
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xfer.xfer_cmd.addr_index = addr_index;
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xfer.xfer_cmd.addr_depth = addr_depth;
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xfer.error = 0U;
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xfer.rx_len = 0U;
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xfer.xfer_cmd.cmd_type = I3C_XFER_TYPE_ADDR_ASSIGN;
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xfer.xfer_cmd.def_byte = 0U;
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xfer.xfer_cmd.data_len = 0U;
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i3c_send_xfer_cmd(base, &xfer);
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if (omv_i3c_transfer_wait(base, &xfer, I3C_SCAN_TIMEOUT) != 0) {
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omv_i3c_transfer_end(base);
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return -1;
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}
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return 0;
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}
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int omv_i3c_assign(omv_i2c_t *i3c, uint8_t static_addr, uint8_t *ref_dyn_addr) {
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int32_t pos = 0U;
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I3C_Type *base = i3c->inst;
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/*Returns error if slave static address is invalid */
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if (!static_addr) {
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return -1;
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}
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/* Find the first unused index in freepos, note that this also
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* corresponds to the first unused location in the DAT
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*/
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pos = omv_i3c_gen_dyn_addr(i3c, ref_dyn_addr);
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/* the dat is full */
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if (pos < 0) {
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return -1;
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}
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/* We have space in the dat,
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* program the dat in index pos */
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i3c_add_slv_to_dat(base, pos, *ref_dyn_addr, static_addr);
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if (omv_i3c_send_command_assign(base, I3C_CCC_SETDASA, (uint8_t) pos, 1U) != 0) {
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return -1;
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}
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return 0;
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}
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int omv_i3c_scan_assign(omv_i2c_t *i3c, uint8_t *list, uint8_t size) {
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int32_t pos = 0U;
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uint8_t init_pos = 0xFFU;
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I3C_Type *base = i3c->inst;
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uint8_t dyn_addr = 0U;
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uint8_t iter = 0U;
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for (iter = 0U; iter < size; iter++) {
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pos = omv_i3c_gen_dyn_addr(i3c, &dyn_addr);
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/* the dat is full */
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if (pos < 0) {
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if (init_pos == 0xFFU) {
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return -1;
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} else{
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break;
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}
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} else {
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if (pos >= size) {
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break;
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}
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list[pos] = dyn_addr;
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omv_i3c_add_dyn_addr_parity(&dyn_addr);
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/* We have space in the dat,
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* program the dat in index pos */
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i3c_add_slv_to_dat(base, pos, dyn_addr, 0);
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}
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/* Stores first found free address position in
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* init position*/
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if (init_pos == 0xFFU) {
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init_pos = (uint8_t) pos;
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}
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}
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if (omv_i3c_send_command_assign(base, I3C_CCC_ENTDAA, init_pos, pos + 1) != 0) {
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return -1;
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}
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return 0;
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}
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int omv_i3c_enable(omv_i2c_t *i3c, bool enable) {
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//TODO: For I3C this causes a lockup.
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I3C_Type *base = i3c->inst;
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if (enable) {
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base->I3C_DEVICE_CTRL = base->I3C_DEVICE_CTRL & ~I3C_DEVICE_CTRL_ENABLE;
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while (base->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE) {
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}
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} else {
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base->I3C_DEVICE_CTRL = base->I3C_DEVICE_CTRL | I3C_DEVICE_CTRL_ENABLE;
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while (!(base->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE)) {
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}
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i3c_resume(base);
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}
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return 0;
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}
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int omv_i3c_gencall(omv_i2c_t *i3c, uint8_t cmd) {
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int ret = 0;
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ret |= omv_i3c_write_bytes(i3c, 0, &cmd, 1, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_readb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t *reg_data) {
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int ret = 0;
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, ®_addr, 1, OMV_I2C_XFER_NO_STOP);
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ret |= omv_i3c_read_bytes(i3c, tgt_addr, reg_data, 1, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_writeb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t reg_data) {
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int ret = 0;
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uint8_t buf[] = {reg_addr, reg_data};
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_readb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t *reg_data) {
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int ret = 0;
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uint8_t buf[] = {(reg_addr >> 8), reg_addr};
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
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ret |= omv_i3c_read_bytes(i3c, tgt_addr, reg_data, 1, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_writeb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t reg_data) {
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int ret = 0;
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uint8_t buf[] = {(reg_addr >> 8), reg_addr, reg_data};
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 3, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_readw(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t *reg_data) {
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int ret = 0;
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, ®_addr, 1, OMV_I2C_XFER_NO_STOP);
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ret |= omv_i3c_read_bytes(i3c, tgt_addr, (uint8_t *) reg_data, 2, OMV_I2C_XFER_NO_FLAGS);
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*reg_data = (*reg_data << 8) | (*reg_data >> 8);
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return ret;
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}
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int omv_i3c_writew(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t reg_data) {
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int ret = 0;
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uint8_t buf[] = {reg_addr, (reg_data >> 8), reg_data};
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ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 3, OMV_I2C_XFER_NO_FLAGS);
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return ret;
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}
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int omv_i3c_readw2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t *reg_data) {
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int ret = 0;
|
|
uint8_t buf[] = {(reg_addr >> 8), reg_addr};
|
|
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
|
|
ret |= omv_i3c_read_bytes(i3c, tgt_addr, (uint8_t *) reg_data, 2, OMV_I2C_XFER_NO_FLAGS);
|
|
*reg_data = (*reg_data << 8) | (*reg_data >> 8);
|
|
return ret;
|
|
}
|
|
|
|
int omv_i3c_writew2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t reg_data) {
|
|
int ret = 0;
|
|
uint8_t buf[] = {(reg_addr >> 8), reg_addr, (reg_data >> 8), reg_data};
|
|
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 4, OMV_I2C_XFER_NO_FLAGS);
|
|
return ret;
|
|
}
|
|
|
|
static int omv_i3c_check_transfer(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len) {
|
|
uint8_t addr = tgt_addr >> 1;
|
|
|
|
if (!buf || !len) {
|
|
return -1;
|
|
}
|
|
|
|
if (len > I3C_MAX_DATA_BUF_SIZE) {
|
|
return -1;
|
|
}
|
|
|
|
return omv_i3c_get_addr_pos(i3c, addr);
|
|
}
|
|
|
|
int omv_i3c_read_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags) {
|
|
int32_t index;
|
|
i3c_xfer_t xfer = {0};
|
|
I3C_Type *base = (I3C_Type *) i3c->inst;
|
|
|
|
index = omv_i3c_check_transfer(i3c, tgt_addr, buf, len);
|
|
if (index < 0) {
|
|
return -1;
|
|
}
|
|
|
|
xfer.error = 0U;
|
|
xfer.tx_buf = NULL;
|
|
xfer.tx_len = 0U;
|
|
xfer.xfer_cmd.addr_index = index;
|
|
xfer.xfer_cmd.data_len = len;
|
|
xfer.rx_len = len;
|
|
|
|
xfer.rx_buf = buf;
|
|
|
|
/* Invoke master receive api */
|
|
if (flags & (OMV_I2C_XFER_NO_STOP | OMV_I2C_XFER_SUSPEND)) {
|
|
i3c_master_rx_blocking(base, &xfer);
|
|
} else {
|
|
i3c_master_rx(base, &xfer);
|
|
}
|
|
|
|
if (omv_i3c_transfer_wait(base, &xfer, I3C_XFER_TIMEOUT) != 0) {
|
|
omv_i3c_transfer_end(base);
|
|
return -1;
|
|
}
|
|
|
|
// if (xfer.rx_buf) {
|
|
// for (uint32_t i = 0, dr = 0; i < xfer.rx_len; i++, dr >>= 8) {
|
|
// if ((i % 4) == 0) {
|
|
// dr = base->I3C_RX_DATA_PORT;
|
|
// }
|
|
// xfer.rx_buf[i] = dr & 0xFF;
|
|
// }
|
|
// }
|
|
|
|
return 0;
|
|
}
|
|
|
|
int omv_i3c_write_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags) {
|
|
int32_t index;
|
|
i3c_xfer_t xfer = {0};
|
|
I3C_Type *base = (I3C_Type *) i3c->inst;
|
|
|
|
index = omv_i3c_check_transfer(i3c, tgt_addr, buf, len);
|
|
if (index < 0) {
|
|
return -1;
|
|
}
|
|
|
|
xfer.error = 0U;
|
|
xfer.rx_buf = NULL;
|
|
xfer.rx_len = 0U;
|
|
xfer.xfer_cmd.addr_index = index;
|
|
xfer.xfer_cmd.data_len = len;
|
|
|
|
xfer.tx_buf = buf;
|
|
xfer.tx_len = len;
|
|
|
|
/* Invoke master send api */
|
|
if (flags & (OMV_I2C_XFER_NO_STOP | OMV_I2C_XFER_SUSPEND)) {
|
|
i3c_master_tx_blocking(base, &xfer);
|
|
} else {
|
|
i3c_master_tx(base, &xfer);
|
|
}
|
|
|
|
if (omv_i3c_transfer_wait(base, &xfer, I3C_XFER_TIMEOUT) != 0) {
|
|
omv_i3c_transfer_end(base);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int omv_i3c_pulse_scl(omv_i2c_t *i3c) {
|
|
if (i3c->initialized && i3c->scl_pin) {
|
|
omv_i3c_deinit(i3c);
|
|
omv_gpio_config(i3c->scl_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
|
// Pulse SCL to recover stuck device.
|
|
for (int i = 0; i < 1000; i++) {
|
|
omv_gpio_write(i3c->scl_pin, 1);
|
|
mp_hal_delay_us(10);
|
|
omv_gpio_write(i3c->scl_pin, 0);
|
|
mp_hal_delay_us(10);
|
|
}
|
|
omv_i3c_init(i3c, i3c->id, i3c->speed);
|
|
}
|
|
return 0;
|
|
}
|