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PORTENTA: Update FMC/SDRAM and QSPI PLL settings.
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@ -1 +1 @@
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Subproject commit c294f8404c3f21fdc4841636a8a42378365262ef
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Subproject commit 9992c24f3088e5ebe2138f0651cc962cb9439ef6
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@ -87,9 +87,9 @@
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 180MHz for FMC and QSPI.
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (72)
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#define OMV_OSC_PLL2N (80)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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