mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
PORTENTA: Update FMC/SDRAM and QSPI PLL settings.
This commit is contained in:
parent
d332c695d9
commit
112ea40cfe
@ -1 +1 @@
|
|||||||
Subproject commit c294f8404c3f21fdc4841636a8a42378365262ef
|
Subproject commit 9992c24f3088e5ebe2138f0651cc962cb9439ef6
|
||||||
@ -87,9 +87,9 @@
|
|||||||
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
|
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
|
||||||
#define OMV_OSC_PLL1FRAC (0)
|
#define OMV_OSC_PLL1FRAC (0)
|
||||||
|
|
||||||
// PLL2 180MHz for FMC and QSPI.
|
// PLL2 200MHz for FMC and QSPI.
|
||||||
#define OMV_OSC_PLL2M (5)
|
#define OMV_OSC_PLL2M (5)
|
||||||
#define OMV_OSC_PLL2N (72)
|
#define OMV_OSC_PLL2N (80)
|
||||||
#define OMV_OSC_PLL2P (2)
|
#define OMV_OSC_PLL2P (2)
|
||||||
#define OMV_OSC_PLL2Q (2)
|
#define OMV_OSC_PLL2Q (2)
|
||||||
#define OMV_OSC_PLL2R (2)
|
#define OMV_OSC_PLL2R (2)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user