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drivers/pixart: Switch to the new SPI HAL.
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parent
5bbccf9d8f
commit
8c1cb53c65
@ -10,95 +10,107 @@
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* Pixart SPI driver.
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* Pixart SPI driver.
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*/
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*/
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#include "omv_boardconfig.h"
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#include "omv_boardconfig.h"
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#ifdef ISC_SPI
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#ifdef ISC_SPI_ID
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <stdbool.h>
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#include <stdbool.h>
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#include STM32_HAL_H
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#include "common.h"
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#include "common.h"
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#include "omv_gpio.h"
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#include "omv_gpio.h"
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#include "omv_spi.h"
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#include "pixspi.h"
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#include "pixspi.h"
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#define SPI_TIMEOUT (5000) // in ms
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#define SPI_BUS_TIMEOUT (5000) // in ms
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#ifdef PIXART_SPI_DEBUG
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#define debug_printf(...) printf(__VA_ARGS__)
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#else
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#define debug_printf(...)
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#endif
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extern SPI_HandleTypeDef ISC_SPIHandle;
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static omv_spi_t spi_bus;
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static bool spi_send(uint8_t *data, uint16_t len)
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static bool spi_send(uint8_t *txbuf, uint16_t len)
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{
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{
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HAL_StatusTypeDef status = HAL_OK;
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int ret = 0;
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omv_gpio_write(ISC_SPI_SSEL_PIN, 0);
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// mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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status = HAL_SPI_Transmit(
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&ISC_SPIHandle, data, len, SPI_TIMEOUT);
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// MICROPY_END_ATOMIC_SECTION(atomic_state);
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omv_gpio_write(ISC_SPI_SSEL_PIN, 1);
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return (status == HAL_OK);
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omv_spi_transfer_t spi_xfer = {
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.txbuf = txbuf,
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.rxbuf = NULL,
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.size = len,
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.timeout = SPI_BUS_TIMEOUT,
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.flags = OMV_SPI_XFER_BLOCKING,
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.callback = NULL,
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.userdata = NULL,
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};
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omv_gpio_write(spi_bus.cs, 0);
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ret = omv_spi_transfer_start(&spi_bus, &spi_xfer);
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omv_gpio_write(spi_bus.cs, 1);
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return ret;
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}
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}
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static bool spi_send_recv(uint8_t *txData, uint8_t *rxData, uint16_t len)
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static bool spi_send_recv(uint8_t *txbuf, uint8_t *rxbuf, uint16_t len)
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{
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{
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omv_gpio_write(ISC_SPI_SSEL_PIN, 0);
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int ret = 0;
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// mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
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bool res = (HAL_SPI_Transmit(&ISC_SPIHandle, txData, 1, SPI_TIMEOUT) == HAL_OK);
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omv_spi_transfer_t spi_xfer = {
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res = (HAL_SPI_Receive(&ISC_SPIHandle, rxData, len, SPI_TIMEOUT) == HAL_OK);
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.timeout = SPI_BUS_TIMEOUT,
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// MICROPY_END_ATOMIC_SECTION(atomic_state);
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.flags = OMV_SPI_XFER_BLOCKING,
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omv_gpio_write(ISC_SPI_SSEL_PIN, 1);
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.callback = NULL,
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return res;
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.userdata = NULL,
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};
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omv_gpio_write(spi_bus.cs, 0);
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spi_xfer.size = 1;
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spi_xfer.txbuf = txbuf;
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spi_xfer.rxbuf = NULL;
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ret |= omv_spi_transfer_start(&spi_bus, &spi_xfer);
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spi_xfer.size = len;
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spi_xfer.txbuf = NULL;
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spi_xfer.rxbuf = rxbuf;
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ret |= omv_spi_transfer_start(&spi_bus, &spi_xfer);
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omv_gpio_write(spi_bus.cs, 1);
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return ret;
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}
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}
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bool pixspi_init()
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bool pixspi_init()
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{
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{
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// Init SPI
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// Init SPI
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memset(&ISC_SPIHandle, 0, sizeof(ISC_SPIHandle));
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omv_spi_config_t spi_config;
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ISC_SPIHandle.Instance = ISC_SPI;
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omv_spi_default_config(&spi_config, ISC_SPI_ID);
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ISC_SPIHandle.Init.Mode = SPI_MODE_MASTER;
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ISC_SPIHandle.Init.Direction = SPI_DIRECTION_2LINES;
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ISC_SPIHandle.Init.DataSize = SPI_DATASIZE_8BIT;
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ISC_SPIHandle.Init.CLKPolarity = SPI_POLARITY_HIGH;
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ISC_SPIHandle.Init.CLKPhase = SPI_PHASE_2EDGE;
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ISC_SPIHandle.Init.NSS = SPI_NSS_SOFT;
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ISC_SPIHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32 ;
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ISC_SPIHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
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ISC_SPIHandle.Init.TIMode = SPI_TIMODE_DISABLED;
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ISC_SPIHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
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ISC_SPIHandle.Init.CRCPolynomial = 0;
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if (HAL_SPI_Init(&ISC_SPIHandle) != HAL_OK) {
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spi_config.baudrate = 5000000;
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// Initialization Error
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spi_config.nss_enable = false; // Soft NSS
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spi_config.clk_pol = OMV_SPI_CPOL_HIGH;
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spi_config.clk_pha = OMV_SPI_CPHA_2EDGE;
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if (omv_spi_init(&spi_bus, &spi_config) != 0) {
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return false;
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return false;
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}
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}
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// Re-Init GPIO for SPI SS(CS) pin, software control.
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omv_gpio_config(ISC_SPI_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
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// Default high.
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omv_gpio_write(ISC_SPI_SSEL_PIN, 1);
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return true;
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return true;
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}
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}
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void pixspi_release()
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void pixspi_release()
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{
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{
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omv_gpio_write(ISC_SPI_SSEL_PIN, 0);
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omv_gpio_write(spi_bus.cs, 1);
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HAL_SPI_DeInit(&ISC_SPIHandle);
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omv_spi_deinit(&spi_bus);
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}
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}
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int pixspi_regs_read(uint8_t addr, uint8_t * data, uint16_t length)
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int pixspi_regs_read(uint8_t addr, uint8_t * data, uint16_t length)
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{
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{
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if ((addr & 0x80)) {
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if ((addr & 0x80)) {
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#ifdef DEBUG
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debug_printf("pixspi_regs_read() address (0x%x) overflow.\n", addr);
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printf("pixspi_regs_read() address (0x%x) overflow.\n", addr);
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#endif
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return -1;
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return -1;
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}
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}
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addr |= 0x80;
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addr |= 0x80;
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if (!spi_send_recv(&addr, data, length)) {
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if (!spi_send_recv(&addr, data, length)) {
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#ifdef DEBUG
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debug_printf("spi_send_recv() failed.\n");
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printf("spi_send_recv() failed.\n");
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#endif
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return -1;
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return -1;
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}
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}
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return 0;
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return 0;
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@ -108,9 +120,7 @@ int pixspi_regs_write(uint8_t addr, const uint8_t * data, uint16_t length)
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{
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{
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uint8_t buff[64] = {};
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uint8_t buff[64] = {};
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if ((addr & 0x80) == 0x80) {
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if ((addr & 0x80) == 0x80) {
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#ifdef DEBUG
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debug_printf("pixspi_regs_read() address (0x%x) overflow.\n", addr);
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printf("pixspi_regs_read() address (0x%x) overflow.\n", addr);
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#endif
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return -1;
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return -1;
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}
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}
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int32_t remaining = length;
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int32_t remaining = length;
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@ -122,9 +132,7 @@ int pixspi_regs_write(uint8_t addr, const uint8_t * data, uint16_t length)
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memcpy(buff+1, data, len);
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memcpy(buff+1, data, len);
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bool res = spi_send(buff, len + 1);
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bool res = spi_send(buff, len + 1);
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if (!res) {
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if (!res) {
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#ifdef DEBUG
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debug_printf("spi_send() failed.\n");
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printf("spi_send() failed.\n");
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#endif
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return -1;
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return -1;
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}
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}
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remaining = remaining - MAX_LENGTH;
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remaining = remaining - MAX_LENGTH;
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@ -62,7 +62,7 @@
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_PAJ6100 (0)
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#define OMV_ENABLE_PAJ6100 (1)
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#define OMV_ENABLE_FROGEYE2020 (1)
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#define OMV_ENABLE_FROGEYE2020 (1)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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@ -163,7 +163,7 @@
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (100K) // minimum fb alloc size
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#define OMV_FB_ALLOC_SIZE (100K) // minimum fb alloc size
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#define OMV_STACK_SIZE (64K)
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (229K)
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#define OMV_HEAP_SIZE (228K)
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#define OMV_LINE_BUF_SIZE (5 * 1024) // Image line buffer.
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#define OMV_LINE_BUF_SIZE (5 * 1024) // Image line buffer.
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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@ -61,7 +61,7 @@
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_PAJ6100 (0)
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#define OMV_ENABLE_PAJ6100 (1)
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#define OMV_ENABLE_FROGEYE2020 (1)
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#define OMV_ENABLE_FROGEYE2020 (1)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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