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https://github.com/openmv/openmv.git
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commit
a2ddbb6563
@ -76,6 +76,9 @@
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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// PLL1 400MHz/40MHz for SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (5)
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@ -15,22 +15,42 @@
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#include STM32_HAL_H
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#include "py_cpufreq.h"
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#include "py_helper.h"
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#include "omv_boardconfig.h"
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#if defined(STM32F7) || defined(STM32H7)
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#define ARRAY_LENGTH(x) (sizeof(x)/sizeof(x[0]))
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#if defined(STM32H7)
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static const uint32_t cpufreq_freqs[] = {120, 240, 480};
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#define N_FREQUENCIES (4)
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static const uint32_t CPUFREQ_FREQS_REV_V [N_FREQUENCIES] = {60, 120, 240, 480};
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static const uint32_t CPUFREQ_FREQS_REV_XY[N_FREQUENCIES] = {50, 100, 200, 400};
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#elif defined(STM32F7)
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static const uint32_t cpufreq_pllq[] = {5, 6, 7, 8, 9};
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static const uint32_t cpufreq_freqs[] = {120, 144, 168, 192, 216};
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static const uint32_t cpufreq_latency[] = { // Flash latency (see table 11)
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#define N_FREQUENCIES (5)
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static const uint32_t cpufreq_pllq[N_FREQUENCIES] = {5, 6, 7, 8, 9};
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static const uint32_t cpufreq_freqs[N_FREQUENCIES] = {120, 144, 168, 192, 216};
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static const uint32_t cpufreq_latency[N_FREQUENCIES] = { // Flash latency (see table 11)
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FLASH_LATENCY_3, FLASH_LATENCY_4, FLASH_LATENCY_5, FLASH_LATENCY_7, FLASH_LATENCY_7
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};
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#endif
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uint32_t cpufreq_get_cpuclk()
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#if defined(STM32H7)
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static const uint32_t *cpufreq_get_frequencies()
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{
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#if (OMV_MAX_CPU_FREQ == 400)
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(void)CPUFREQ_FREQS_REV_V;
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// If the maximum frequency is set to 400 use rev x/y frequencies.
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return CPUFREQ_FREQS_REV_XY;
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#else
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// Otherwise, determine the frequencies dynamically using the revid.
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if (HAL_GetREVID() >= 0x2003) {
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return CPUFREQ_FREQS_REV_V;
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} else {
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return CPUFREQ_FREQS_REV_XY;
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}
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#endif
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}
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#endif
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static uint32_t cpufreq_get_cpuclk()
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{
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uint32_t cpuclk = HAL_RCC_GetSysClockFreq();
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@ -48,6 +68,9 @@ uint32_t cpufreq_get_cpuclk()
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case RCC_SYSCLK_DIV4:
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cpuclk /= 4;
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break;
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case RCC_SYSCLK_DIV8:
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cpuclk /= 8;
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break;
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default:
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break;
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}
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@ -68,8 +91,11 @@ mp_obj_t py_cpufreq_get_current_frequencies()
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mp_obj_t py_cpufreq_get_supported_frequencies()
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{
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#if defined(STM32H7)
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const uint32_t *cpufreq_freqs = cpufreq_get_frequencies();
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#endif
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mp_obj_t freq_list = mp_obj_new_list(0, NULL);
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for (int i=0; i<ARRAY_LENGTH(cpufreq_freqs); i++) {
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for (int i=0; i<N_FREQUENCIES; i++) {
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mp_obj_list_append(freq_list, mp_obj_new_int(cpufreq_freqs[i]));
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}
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return freq_list;
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@ -85,7 +111,10 @@ mp_obj_t py_cpufreq_set_frequency(mp_obj_t cpufreq_obj)
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// Check if frequency is supported
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int cpufreq_idx = -1;
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uint32_t cpufreq = mp_obj_get_int(cpufreq_obj);
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for (int i=0; i<ARRAY_LENGTH(cpufreq_freqs); i++) {
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#if defined(STM32H7)
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const uint32_t *cpufreq_freqs = cpufreq_get_frequencies();
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#endif
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for (int i=0; i<N_FREQUENCIES; i++) {
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if (cpufreq == cpufreq_freqs[i]) {
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cpufreq_idx = i;
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break;
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@ -109,6 +138,17 @@ mp_obj_t py_cpufreq_set_frequency(mp_obj_t cpufreq_obj)
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RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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switch (cpufreq) {
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case 50:
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case 60:
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV8; // D1CPRE
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; // HPRE
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; // D2PPRE1
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; // D2PPRE2
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; // D1PPRE
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; // D3PPRE
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break;
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case 100:
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case 120:
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV4; // D1CPRE
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; // HPRE
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@ -118,6 +158,7 @@ mp_obj_t py_cpufreq_set_frequency(mp_obj_t cpufreq_obj)
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; // D3PPRE
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break;
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case 200:
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case 240:
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV2; // D1CPRE
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; // HPRE
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@ -127,6 +168,7 @@ mp_obj_t py_cpufreq_set_frequency(mp_obj_t cpufreq_obj)
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; // D3PPRE
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break;
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case 400:
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case 480:
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; // D1CPRE
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; // HPRE
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