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ports/stm32: Clean up board Make flags.
This commit is contained in:
parent
05bd219b12
commit
ac9a96809c
@ -61,7 +61,7 @@
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uint32_t SystemCoreClock = 16000000;
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extern void __fatal_error(const char *msg);
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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#define SRAM_BASE D1_AXISRAM_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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@ -73,7 +73,7 @@ extern void __fatal_error(const char *msg);
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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#elif defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#elif defined(STM32F4) || defined(STM32F7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
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@ -102,7 +102,6 @@ void SystemInit(void)
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signal is detectable by the CPU after a WFI/WFE instruction. */
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//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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#if !defined(CORE_CM4)
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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@ -116,7 +115,7 @@ void SystemInit(void)
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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@ -146,39 +145,37 @@ void SystemInit(void)
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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#endif // defined(MCU_SERIES_H7)
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#endif // defined(STM32H7)
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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RCC->CIR = 0x00000000;
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#elif defined(MCU_SERIES_L4) || defined(MCU_SERIES_H7)
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#elif defined(STM32L4) || defined(STM32H7)
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RCC->CIER = 0x00000000;
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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// See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif // defined(MCU_SERIES_H7)
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#endif // defined(STM32H7)
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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#if !defined(NDEBUG)
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEP;
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#elif defined(MCU_SERIES_H7)
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#elif defined(STM32H7)
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DBGMCU->CR |= DBGMCU_CR_DBG_SLEEPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STOPD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
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#endif
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#endif
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#endif // !defined(CORE_CM4)
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/* Configure the Vector Table location add offset address ------------------*/
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SCB->VTOR = OMV_VTOR_BASE;
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}
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@ -187,11 +184,11 @@ void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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/* Supply configuration update enable */
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HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
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#else
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@ -202,7 +199,7 @@ void SystemClock_Config(void)
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// Enable VSCALE0 for revision V devices.
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if (HAL_GetREVID() >= 0x2003) {
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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@ -215,7 +212,7 @@ void SystemClock_Config(void)
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}
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// Wait for PWR_FLAG_VOSRDY
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET) {
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}
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#endif
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@ -264,7 +261,7 @@ void SystemClock_Config(void)
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RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
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RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// Override PLL1 frequency for revision Y devices,
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// with maximum frequency of 400MHz CPU 200MHz Bus.
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if (HAL_GetREVID() < 0x2003) {
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@ -314,7 +311,7 @@ void SystemClock_Config(void)
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PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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#if !defined(OMV_OMVPT_ERRATA_RTC)
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PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC;
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@ -385,9 +382,9 @@ void SystemClock_Config(void)
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// Initialization Error
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__fatal_error("HAL_RCCEx_PeriphCLKConfig");
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}
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#endif // defined(MCU_SERIES_H7)
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#endif // defined(STM32H7)
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
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// Initialization Error
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__fatal_error("HAL_PWREx_EnableOverDrive");
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@ -395,7 +392,7 @@ void SystemClock_Config(void)
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#endif
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/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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@ -418,7 +415,7 @@ void SystemClock_Config(void)
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__fatal_error("HAL_RCC_ClockConfig");
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}
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// Activate CSI clock mondatory for I/O Compensation Cell
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__HAL_RCC_CSI_ENABLE() ;
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@ -63,16 +63,12 @@ export FROZEN_MANIFEST
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# Export board config variables
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export PORT
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export MCU
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export MCU_SERIES
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export MCU_VARIANT
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export MCU_CORE
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# Export Directories
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export TOP_DIR
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export BUILD
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export TOOLS
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export FW_DIR
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export HAL_DIR
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export BOOT_DIR
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export OMV_DIR
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export CMSIS_DIR
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@ -80,7 +80,7 @@ void omv_csi_mdma_irq_handler(void) {
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static int omv_csi_dma_config() {
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// DMA Stream configuration
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DMAHandle.Instance = DMA2_Stream1;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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DMAHandle.Init.Request = DMA_REQUEST_DCMI; /* DMA Channel */
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#else
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DMAHandle.Init.Channel = DMA_CHANNEL_1; /* DMA Channel */
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@ -215,7 +215,7 @@ int omv_csi_config(omv_csi_config_t config) {
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DCMIHandle.Init.CaptureRate = DCMI_CR_ALL_FRAME; // Capture rate all frames
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DCMIHandle.Init.ExtendedDataMode = DCMI_EXTEND_DATA_8B; // Capture 8 bits on every pixel clock
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DCMIHandle.Init.JPEGMode = DCMI_JPEG_DISABLE;
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#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
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#if defined(STM32F7) || defined(STM32H7)
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DCMIHandle.Init.ByteSelectMode = DCMI_BSM_ALL; // Capture all received bytes
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DCMIHandle.Init.ByteSelectStart = DCMI_OEBS_ODD; // Ignored
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DCMIHandle.Init.LineSelectMode = DCMI_LSM_ALL; // Capture all received lines
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@ -73,7 +73,7 @@ int omv_gpu_draw_image(image_t *src_img,
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}
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// DMA2D must always fetch the background on the F4 and F7 series so do this in software.
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
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#if defined(STM32F4) || defined(STM32F7)
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if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
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return -1;
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}
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@ -91,7 +91,7 @@ int omv_gpu_draw_image(image_t *src_img,
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dma2d.Init.Mode = DMA2D_M2M_BLEND;
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}
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
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dma2d.Init.Mode = DMA2D_M2M_BLEND_BG;
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}
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@ -202,7 +202,7 @@ int omv_gpu_draw_image(image_t *src_img,
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uint32_t dst = (uint32_t) dst16;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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if (hint & IMAGE_HINT_BLACK_BACKGROUND) {
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dst = 0;
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}
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@ -21,12 +21,13 @@
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# THE SOFTWARE.
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# Set startup and system files for CMSIS Makefile.
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SYSTEM ?= st/system_stm32fxxx
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STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
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BOOT_DIR := boot
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LDSCRIPT ?= stm32fxxx
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SYSTEM ?= st/system_stm32fxxx
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LDSCRIPT ?= stm32fxxx
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STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
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MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
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MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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HAL_DIR = hal/stm32/$(MCU_SERIES)
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# Compiler Flags
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CFLAGS += -std=gnu99 \
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@ -43,19 +44,18 @@ CFLAGS += -std=gnu99 \
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-mcpu=$(CPU) \
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-mtune=$(CPU) \
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-mfpu=$(FPU) \
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-mfloat-abi=hard \
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-D$(CFLAGS_MCU)
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-mfloat-abi=hard
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CFLAGS += -D$(MCU) \
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-D$(TARGET) \
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-DARM_NN_TRUNCATE \
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-D__FPU_PRESENT=1 \
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-D__VFP_FP__ \
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-DUSE_FULL_LL_DRIVER \
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-DHSE_VALUE=$(OMV_HSE_VALUE)\
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-DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \
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-DSTM32_HAL_H=$(HAL_INC) \
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-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
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-DUSE_FULL_LL_DRIVER \
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-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
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-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
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$(OMV_BOARD_CFLAGS)
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# Linker Flags
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@ -95,7 +95,7 @@ DEFINE_SPI_INSTANCE(6)
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static omv_spi_t *omv_spi_descr_all[6] = { NULL };
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static uint32_t omv_spi_clocksource(SPI_TypeDef *spi) {
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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if (spi == SPI1 || spi == SPI2 || spi == SPI3) {
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return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
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} else if (spi == SPI4 || spi == SPI5) {
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@ -290,7 +290,7 @@ static int omv_spi_dma_init(omv_spi_t *spi, uint32_t direction, omv_spi_config_t
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dma_descr->Init.MemBurst = DMA_MBURST_SINGLE;
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dma_descr->Init.PeriphBurst = DMA_PBURST_SINGLE;
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dma_descr->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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dma_descr->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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#else
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dma_descr->Init.PeriphDataAlignment = (config->datasize == 8) ? DMA_PDATAALIGN_BYTE : DMA_PDATAALIGN_HALFWORD;
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@ -336,9 +336,9 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) {
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spi_descr->Init.CLKPhase = config->clk_pha;
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spi_descr->Init.CLKPolarity = config->clk_pol;
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spi_descr->Init.BaudRatePrescaler = omv_spi_prescaler(spi_descr->Instance, config->baudrate);
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#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
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#if defined(STM32F7) || defined(STM32H7)
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spi_descr->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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spi_descr->Init.NSSPolarity = (config->nss_pol == 0) ? SPI_NSS_POLARITY_LOW : SPI_NSS_POLARITY_HIGH;
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spi_descr->Init.FifoThreshold = SPI_FIFO_THRESHOLD_04DATA;
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spi_descr->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
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@ -356,7 +356,7 @@ static int omv_spi_bus_init(omv_spi_t *spi, omv_spi_config_t *config) {
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} else if (config->bus_mode == OMV_SPI_BUS_RX) {
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spi_descr->Init.Direction = SPI_DIRECTION_2LINES_RXONLY;
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} else {
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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spi_descr->Init.Direction = SPI_DIRECTION_2LINES_TXONLY;
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#else
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spi_descr->Init.Direction = SPI_DIRECTION_1LINE;
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@ -92,7 +92,7 @@ void HAL_MspInit(void) {
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#endif // defined(OMV_DMA_MEMORY)
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// Enable I/D cache.
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#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
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#if defined(STM32F7) || defined(STM32H7)
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#ifdef OMV_DISABLE_CACHE
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// Disable caches for testing.
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SCB_DisableICache();
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@ -147,7 +147,7 @@ void HAL_MspInit(void) {
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__DMA1_CLK_ENABLE();
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__DMA2_CLK_ENABLE();
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// MDMA clock.
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__HAL_RCC_MDMA_CLK_ENABLE();
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NVIC_SetPriority(MDMA_IRQn, IRQ_PRI_MDMA);
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@ -212,7 +212,7 @@ void HAL_MspInit(void) {
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omv_gpio_write(OMV_FIR_LEPTON_POWER_PIN, 0);
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// This disconnects PA0/PA1 from PA0_C/PA1_C.
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// PA0_C/PA1_C connect to ADC1/2 Channels P0/P1
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HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_OPEN);
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@ -435,7 +435,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
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return;
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}
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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omv_gpio_config(spi_pins.sclk_pin, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1);
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#else
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// The STM32F4 and STM32F7 don't set the initial state of the clock line until transmitting the
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@ -453,7 +453,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) {
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} else {
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if (hspi->Init.Mode == SPI_MODE_MASTER) {
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omv_gpio_config(spi_pins.ssel_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_HIGH, -1);
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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if (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW) {
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omv_gpio_write(spi_pins.ssel_pin, 1);
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} else {
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@ -80,7 +80,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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#endif
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#if defined(MCU_SERIES_H7)
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#if defined(STM32H7)
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// Keep USB clock running during sleep or else __WFI() will disable the USB
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__HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE();
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__HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE();
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