Merge pull request #1159 from openmv/pll_clksource

Make PLL clock source configurable.
This commit is contained in:
Ibrahim Abd Elkader 2021-02-12 00:21:09 +02:00 committed by GitHub
commit c756891e74
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8 changed files with 24 additions and 7 deletions

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@ -217,6 +217,9 @@ void SystemClock_Config(void)
}
#endif
/* Macro to configure the PLL clock source */
__HAL_RCC_PLL_PLLSOURCE_CONFIG(OMV_OSC_PLL_CLKSOURCE);
/* Enable HSE Oscillator and activate PLL with HSE as source */
#if defined(OMV_OSC_HSE_STATE)
RCC_OscInitStruct.HSEState = OMV_OSC_HSE_STATE;
@ -225,6 +228,7 @@ void SystemClock_Config(void)
#if defined(OMV_OSC_HSI_STATE)
RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
#endif
#if defined(OMV_OSC_CSI_STATE)
RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
@ -236,7 +240,7 @@ void SystemClock_Config(void)
#endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLSource = OMV_OSC_PLL_CLKSOURCE;
RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
RCC_OscInitStruct.PLL.PLLN = OMV_OSC_PLL1N;
RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;

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@ -42,6 +42,9 @@
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
// Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_5)

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@ -88,6 +88,9 @@
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
// Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)

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@ -89,6 +89,9 @@
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE (RCC_PLLSOURCE_HSE)
// Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)

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@ -116,6 +116,7 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3

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@ -120,6 +120,7 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3

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@ -86,12 +86,6 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// Clock Sources
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
//PLL1 48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3)
#define OMV_OSC_PLL1N (240)
@ -122,6 +116,13 @@
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
// HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)

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@ -118,6 +118,7 @@
#define OMV_OSC_PLL3FRAC (0)
// Clock Sources
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3