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3 Commits
1a0afd9b1f
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4837556859
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@ -49,6 +49,10 @@
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#include "ll_aton_caches_interface.h"
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#include "ll_aton_reloc_network.h"
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// Due to limitations with the STM32N6 NPU design, the ext_ram_sz memory pool
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// must be in external SDRAM and not in internal SRAM. Forcing a minimum of a
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// 1MB allocation ensures that the ext_ram_sz buffer ends up in SDRAM.
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#define AI_MIN_EXT_RAM_SZ (1048576)
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#define AI_RELOC_ALIGNMENT (32)
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typedef struct ml_backend_state {
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@ -132,6 +136,10 @@ int ml_backend_init_model(py_ml_model_obj_t *model) {
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return -1;
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}
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if (rt.ext_ram_sz) {
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rt.ext_ram_sz = OMV_MAX(rt.ext_ram_sz, AI_MIN_EXT_RAM_SZ);
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}
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// Allocate executable memory.
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state->exec_ram_size = OMV_ALIGN_TO(rt.rt_ram_xip, AI_RELOC_ALIGNMENT);
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state->exec_ram_addr = m_new(uint8_t, state->exec_ram_size + AI_RELOC_ALIGNMENT);
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