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12 Commits
265871bf98
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05857bff44
| Author | SHA1 | Date | |
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05857bff44 | ||
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7a46d0c82e | ||
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b897ec4f16 | ||
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ce18e680b2 | ||
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74faef3a8e | ||
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781a7bf86f | ||
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d2d1a9448f | ||
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c4b0b5a3dc | ||
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110a93695f | ||
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310eeae048 | ||
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9110a21450 |
@ -14,12 +14,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
@ -14,12 +14,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
@ -14,12 +14,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
@ -14,12 +14,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
@ -26,12 +26,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v2_224_small.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
@ -14,18 +14,6 @@
|
||||
"alignment": 32,
|
||||
"profile": "default"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v2_224_small.tflite",
|
||||
"alignment": 32,
|
||||
"profile": "default"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 32,
|
||||
"profile": "default"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/blazeface_front_128.tflite",
|
||||
|
||||
@ -14,12 +14,6 @@
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/yolo_v5_224_nano.tflite",
|
||||
"alignment": 16,
|
||||
"optimize": "Performance"
|
||||
},
|
||||
{
|
||||
"type": "tflite",
|
||||
"path": "{TOP}/lib/models/force_int_quant.tflite",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@ -1,2 +0,0 @@
|
||||
background
|
||||
person
|
||||
Binary file not shown.
@ -1,2 +0,0 @@
|
||||
background
|
||||
person
|
||||
@ -162,6 +162,29 @@ int alif_hal_i2c_init(uint32_t bus_id) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int alif_hal_i3c_init(uint32_t bus_id) {
|
||||
omv_gpio_t scl_pin = NULL;
|
||||
omv_gpio_t sda_pin = NULL;
|
||||
|
||||
switch (bus_id) {
|
||||
#if defined(OMV_I3C0_ID)
|
||||
case OMV_I3C0_ID: {
|
||||
enable_i3c_clock();
|
||||
scl_pin = OMV_I3C0_SCL_PIN;
|
||||
sda_pin = OMV_I3C0_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
omv_gpio_config(scl_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(sda_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_MED, -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int alif_hal_spi_init(uint32_t bus_id, bool nss_enable, uint32_t nss_pol) {
|
||||
typedef struct {
|
||||
omv_gpio_t sclk_pin;
|
||||
|
||||
@ -36,6 +36,7 @@
|
||||
|
||||
void alif_hal_init(void);
|
||||
int alif_hal_i2c_init(uint32_t bus_id);
|
||||
int alif_hal_i3c_init(uint32_t bus_id);
|
||||
int alif_hal_spi_init(uint32_t bus_id, bool nss_enable, uint32_t nss_pol);
|
||||
int alif_hal_spi_deinit(uint32_t bus_id);
|
||||
int alif_hal_pdm_init(uint32_t pdm_id);
|
||||
|
||||
@ -173,6 +173,10 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
|
||||
while (inst->I3C_RESET_CTRL & 0x1) {
|
||||
}
|
||||
|
||||
i3c_master_set_dynamic_addr(inst);
|
||||
|
||||
i3c_master_enable_interrupts(inst);
|
||||
|
||||
// Initialize I2C controller
|
||||
i3c_master_init(inst);
|
||||
|
||||
@ -243,13 +247,13 @@ int omv_i2c_enable(omv_i2c_t *i2c, bool enable) {
|
||||
//TODO: For I3C this causes a lockup.
|
||||
I3C_Type *inst = i2c->inst;
|
||||
if (enable) {
|
||||
inst->I3C_DEVICE_CTRL = inst->I3C_DEVICE_CTRL & ~DEV_CTRL_ENABLE;
|
||||
while (inst->I3C_DEVICE_CTRL & DEV_CTRL_ENABLE) {
|
||||
inst->I3C_DEVICE_CTRL = inst->I3C_DEVICE_CTRL & ~I3C_DEVICE_CTRL_ENABLE;
|
||||
while (inst->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE) {
|
||||
}
|
||||
|
||||
} else {
|
||||
inst->I3C_DEVICE_CTRL = inst->I3C_DEVICE_CTRL | DEV_CTRL_ENABLE;
|
||||
while (!(inst->I3C_DEVICE_CTRL & DEV_CTRL_ENABLE)) {
|
||||
inst->I3C_DEVICE_CTRL = inst->I3C_DEVICE_CTRL | I3C_DEVICE_CTRL_ENABLE;
|
||||
while (!(inst->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE)) {
|
||||
}
|
||||
i3c_resume(inst);
|
||||
}
|
||||
@ -397,22 +401,31 @@ static int omv_i2c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32
|
||||
|
||||
static int omv_i3c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32_t timeout) {
|
||||
int ret = 0;
|
||||
I3C_XFER i3c_xfer = {0};
|
||||
i3c_xfer_t i3c_xfer = {0};
|
||||
I3C_Type *base = i2c->inst;
|
||||
|
||||
i3c_add_slv_to_dat(base, I2C_DAT_INDEX, 0, xfer->address);
|
||||
|
||||
i3c_xfer.xfer_cmd.speed = I3C_SPEED_SDR0;
|
||||
// i3c_xfer.addr = xfer->address;
|
||||
|
||||
i3c_xfer.xfer_cmd.addr_index = I2C_DAT_INDEX;
|
||||
// i3c_xfer.xfer_cmd.addr_depth = 1U;
|
||||
i3c_xfer.xfer_cmd.data_len = xfer->size;
|
||||
|
||||
if (xfer->direction == I2C_TRANSFER_READ) {
|
||||
i3c_xfer.rx_buf = xfer->data;
|
||||
i3c_xfer.rx_len = xfer->size;
|
||||
i3c_master_rx(base, &i3c_xfer, I2C_DAT_INDEX, i3c_xfer.rx_len);
|
||||
i3c_master_rx(base, &i3c_xfer);
|
||||
} else {
|
||||
i3c_xfer.tx_buf = xfer->data;
|
||||
i3c_xfer.tx_len = xfer->size;
|
||||
i3c_master_tx(base, &i3c_xfer, I2C_DAT_INDEX, i3c_xfer.tx_len);
|
||||
i3c_master_tx(base, &i3c_xfer);
|
||||
}
|
||||
|
||||
// Wait for the transfer to finish.
|
||||
mp_uint_t tick_start = mp_hal_ticks_ms();
|
||||
/* Waits till some response received */
|
||||
while (base->I3C_INTR_STATUS == 0) {
|
||||
if ((mp_hal_ticks_ms() - tick_start) >= timeout) {
|
||||
// Should not raise exception as we're not always in nlr context.
|
||||
@ -426,7 +439,7 @@ static int omv_i3c_transfer_timeout(omv_i2c_t *i2c, i2c_transfer_t *xfer, uint32
|
||||
// See Table 15-81 Response Data Structure
|
||||
uint32_t resp = base->I3C_RESPONSE_QUEUE_PORT;
|
||||
|
||||
if ((status & INTR_TRANSFER_ERR_STAT) || RESPONSE_PORT_ERR_STATUS(resp)) {
|
||||
if ((status & I3C_INTR_STATUS_TRANSFER_ERR_STS) || I3C_RESPONSE_QUEUE_PORT_ERR_STATUS(resp)) {
|
||||
ret = -1;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
542
ports/alif/omv_i3c.c
Normal file
542
ports/alif/omv_i3c.c
Normal file
@ -0,0 +1,542 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Alif I3C driver.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "py/mphal.h"
|
||||
#include "py/runtime.h"
|
||||
|
||||
#include "omv_portconfig.h"
|
||||
#include "omv_boardconfig.h"
|
||||
#include "alif_hal.h"
|
||||
#include "omv_gpio.h"
|
||||
#include "omv_common.h"
|
||||
#include "omv_i3c.h"
|
||||
#include "sys_ctrl_i3c.h"
|
||||
|
||||
#define I3C_SCAN_TIMEOUT (10)
|
||||
#define I3C_XFER_TIMEOUT (1000)
|
||||
|
||||
/* I3C CCC (Common Command Codes) related definitions */
|
||||
#define I3C_CCC_DIRECT BIT(7)
|
||||
|
||||
#define I3C_CCC_ID(id, broadcast) ((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
|
||||
|
||||
/* Commands valid in both broadcast and unicast modes */
|
||||
#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
|
||||
#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
|
||||
#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
|
||||
#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
|
||||
#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
|
||||
#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
|
||||
#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
|
||||
#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
|
||||
|
||||
/* Broadcast-only commands */
|
||||
#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
|
||||
#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
|
||||
#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
|
||||
#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
|
||||
#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true)
|
||||
|
||||
/* Unicast-only commands */
|
||||
#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
|
||||
#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
|
||||
#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
|
||||
#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
|
||||
#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
|
||||
#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
|
||||
#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
|
||||
#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
|
||||
#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
|
||||
#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
|
||||
#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
|
||||
#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
|
||||
#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
|
||||
|
||||
/* List of some Defining byte values */
|
||||
#define I3C_CCC_DEF_BYTE_SYNC_TICK 0x7F
|
||||
#define I3C_CCC_DEF_BYTE_DELAY_TIME 0xBF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE0 0xDF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE1 0xEF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE2 0xF7
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE3 0xFB
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_TRIG 0xFD
|
||||
#define I3C_CCC_DEF_BYTE_TPH 0x3F
|
||||
#define I3C_CCC_DEF_BYTE_TU 0x9F
|
||||
#define I3C_CCC_DEF_BYTE_ODR 0x8F
|
||||
|
||||
int omv_i3c_init(omv_i2c_t *i3c, uint32_t bus_id, uint32_t speed) {
|
||||
i3c->id = bus_id;
|
||||
i3c->initialized = false;
|
||||
i3c->cw_size = 0;
|
||||
i3c->speed = speed;
|
||||
|
||||
switch (speed) {
|
||||
case OMV_I3C_SPEED_SDR:
|
||||
speed = I3C_BUS_SDR0_SCL_RATE; // 12.5 Mbit/s
|
||||
break;
|
||||
case OMV_I3C_SPEED_HDR:
|
||||
speed = I3C_BUS_MAX_I3C_SCL_RATE; // 12.9 kbit/s
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
switch (bus_id) {
|
||||
#if defined(OMV_I3C0_ID)
|
||||
case OMV_I3C0_ID: {
|
||||
i3c->inst = (I3C_Type *) I3C_BASE;
|
||||
i3c->scl_pin = OMV_I3C0_SCL_PIN;
|
||||
i3c->sda_pin = OMV_I3C0_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
alif_hal_i3c_init(bus_id);
|
||||
|
||||
// I3C controller in non-legacy mode.
|
||||
I3C_Type *base = i3c->inst;
|
||||
|
||||
// Core soft-reset.
|
||||
base->I3C_RESET_CTRL = 0x1;
|
||||
while (base->I3C_RESET_CTRL & 0x1) {
|
||||
}
|
||||
|
||||
i3c_master_set_dynamic_addr(base);
|
||||
|
||||
i3c_master_enable_interrupts(base);
|
||||
|
||||
/* Sets Slave Interrupt Request acceptability at master side */
|
||||
i3c_master_setup_slv_intr_req_ctrl(base, false);
|
||||
|
||||
/* Sets Master Request acceptability at master side */
|
||||
i3c_master_setup_mst_req_ctrl(base, false);
|
||||
|
||||
/* Sets up HJ acceptability at master side */
|
||||
i3c_master_setup_hot_join_ctrl(base, false);
|
||||
|
||||
// Initialize I2C controller
|
||||
i3c_master_init(base);
|
||||
|
||||
// Initialize I3C controller
|
||||
i3c_master_init(base);
|
||||
|
||||
// Configure clock and speed.
|
||||
i3c_normal_bus_clk_cfg(base, speed);
|
||||
|
||||
i3c->initialized = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_deinit(omv_i2c_t *i3c) {
|
||||
if (i3c->initialized) {
|
||||
// TODO
|
||||
i3c->initialized = false;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omv_i3c_get_addr_pos(omv_i2c_t *i3c, uint8_t addr) {
|
||||
size_t pos;
|
||||
|
||||
for (pos = 0; pos < i3c->cw_size; pos++) {
|
||||
if (addr == i3c->cw_buf[pos]) {
|
||||
return (int) pos;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void omv_i3c_add_dyn_addr_parity(uint8_t *dyn_addr) {
|
||||
uint8_t bit_iter = 0U;
|
||||
uint8_t xor_value = 0U;
|
||||
|
||||
/* XOR the 1st 7 bits of dynamic address*/
|
||||
xor_value = ((*dyn_addr) & (1U << 0U));
|
||||
|
||||
for (bit_iter = 1U; bit_iter < 7U; bit_iter++) {
|
||||
xor_value ^= (((*dyn_addr) >> bit_iter) & 1U);
|
||||
}
|
||||
|
||||
/* Assign the negated XOR value to 7th
|
||||
* bit of dynamic address */
|
||||
*dyn_addr |= ((~xor_value) << 7U);
|
||||
}
|
||||
|
||||
static int32_t omv_i3c_gen_dyn_addr(omv_i2c_t *i3c, uint8_t *ref_dyn_addr) {
|
||||
if (i3c->cw_size >= I3C_MAX_DEVS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* we start assigning addresses from 0x09 */
|
||||
*ref_dyn_addr = (uint8_t) i3c->cw_size + I3C_NEXT_SLAVE_ADDR_OFFSET;
|
||||
while (true) {
|
||||
/* Checks if new address is not a self address and
|
||||
* not already assigned to some slave. If true then,
|
||||
* assign it otherwise increment it */
|
||||
if ((omv_i3c_get_addr_pos(i3c, *ref_dyn_addr) < 0) && (i3c_get_dynamic_addr(i3c->inst) != *ref_dyn_addr)) {
|
||||
break;
|
||||
}
|
||||
|
||||
(*ref_dyn_addr)++;
|
||||
}
|
||||
|
||||
i3c->cw_buf[i3c->cw_size] = *ref_dyn_addr;
|
||||
// i3c->cw_buf[i3c->cw_size] &= (~I3C_TARGET_SLAVE_TYPE_I2C);
|
||||
|
||||
return (int32_t) i3c->cw_size++;
|
||||
}
|
||||
|
||||
static int omv_i3c_transfer_wait(I3C_Type *base, i3c_xfer_t *xfer, uint32_t timeout) {
|
||||
// Wait for the transfer to finish.
|
||||
mp_uint_t tick_start = mp_hal_ticks_ms();
|
||||
/* Waits till some response received */
|
||||
while (!(base->I3C_QUEUE_STATUS_LEVEL & I3C_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_Msk)) {
|
||||
if ((mp_hal_ticks_ms() - tick_start) >= timeout) {
|
||||
// Should not raise exception as we're not always in nlr context.
|
||||
return -1;
|
||||
}
|
||||
mp_event_handle_nowait();
|
||||
}
|
||||
|
||||
// See Table 15-81 Response Data Structure
|
||||
uint32_t resp = base->I3C_RESPONSE_QUEUE_PORT;
|
||||
|
||||
if ((I3C_RESPONSE_QUEUE_PORT_ERR_STATUS(resp)) ||
|
||||
(I3C_RESPONSE_QUEUE_PORT_TID(resp) != xfer->xfer_cmd.port_id)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omv_i3c_transfer_end(I3C_Type *base) {
|
||||
i3c_clear_xfer_error(base);
|
||||
i3c_resume(base);
|
||||
}
|
||||
|
||||
static int omv_i3c_send_command_assign(I3C_Type *base, uint8_t cmd_id, uint8_t addr_index, uint8_t addr_depth) {
|
||||
i3c_xfer_t xfer = {0};
|
||||
|
||||
xfer.xfer_cmd.cmd_id = cmd_id;
|
||||
xfer.xfer_cmd.addr_index = addr_index;
|
||||
xfer.xfer_cmd.addr_depth = addr_depth;
|
||||
|
||||
xfer.error = 0U;
|
||||
|
||||
xfer.rx_len = 0U;
|
||||
xfer.xfer_cmd.cmd_type = I3C_XFER_TYPE_ADDR_ASSIGN;
|
||||
xfer.xfer_cmd.def_byte = 0U;
|
||||
xfer.xfer_cmd.data_len = 0U;
|
||||
|
||||
i3c_send_xfer_cmd(base, &xfer);
|
||||
if (omv_i3c_transfer_wait(base, &xfer, I3C_SCAN_TIMEOUT) != 0) {
|
||||
omv_i3c_transfer_end(base);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_assign(omv_i2c_t *i3c, uint8_t static_addr, uint8_t *ref_dyn_addr) {
|
||||
int32_t pos = 0U;
|
||||
I3C_Type *base = i3c->inst;
|
||||
/*Returns error if slave static address is invalid */
|
||||
if (!static_addr) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Find the first unused index in freepos, note that this also
|
||||
* corresponds to the first unused location in the DAT
|
||||
*/
|
||||
pos = omv_i3c_gen_dyn_addr(i3c, ref_dyn_addr);
|
||||
|
||||
/* the dat is full */
|
||||
if (pos < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* We have space in the dat,
|
||||
* program the dat in index pos */
|
||||
i3c_add_slv_to_dat(base, pos, *ref_dyn_addr, static_addr);
|
||||
|
||||
if (omv_i3c_send_command_assign(base, I3C_CCC_SETDASA, (uint8_t) pos, 1U) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_scan_assign(omv_i2c_t *i3c, uint8_t *list, uint8_t size) {
|
||||
int32_t pos = 0U;
|
||||
uint8_t init_pos = 0xFFU;
|
||||
I3C_Type *base = i3c->inst;
|
||||
uint8_t dyn_addr = 0U;
|
||||
uint8_t iter = 0U;
|
||||
|
||||
for (iter = 0U; iter < size; iter++) {
|
||||
pos = omv_i3c_gen_dyn_addr(i3c, &dyn_addr);
|
||||
|
||||
/* the dat is full */
|
||||
if (pos < 0) {
|
||||
if (init_pos == 0xFFU) {
|
||||
return -1;
|
||||
} else{
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (pos >= size) {
|
||||
break;
|
||||
}
|
||||
|
||||
list[pos] = dyn_addr;
|
||||
|
||||
omv_i3c_add_dyn_addr_parity(&dyn_addr);
|
||||
|
||||
/* We have space in the dat,
|
||||
* program the dat in index pos */
|
||||
i3c_add_slv_to_dat(base, pos, dyn_addr, 0);
|
||||
}
|
||||
|
||||
/* Stores first found free address position in
|
||||
* init position*/
|
||||
if (init_pos == 0xFFU) {
|
||||
init_pos = (uint8_t) pos;
|
||||
}
|
||||
}
|
||||
|
||||
if (omv_i3c_send_command_assign(base, I3C_CCC_ENTDAA, init_pos, pos + 1) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_enable(omv_i2c_t *i3c, bool enable) {
|
||||
//TODO: For I3C this causes a lockup.
|
||||
I3C_Type *base = i3c->inst;
|
||||
if (enable) {
|
||||
base->I3C_DEVICE_CTRL = base->I3C_DEVICE_CTRL & ~I3C_DEVICE_CTRL_ENABLE;
|
||||
while (base->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE) {
|
||||
}
|
||||
|
||||
} else {
|
||||
base->I3C_DEVICE_CTRL = base->I3C_DEVICE_CTRL | I3C_DEVICE_CTRL_ENABLE;
|
||||
while (!(base->I3C_DEVICE_CTRL & I3C_DEVICE_CTRL_ENABLE)) {
|
||||
}
|
||||
i3c_resume(base);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_gencall(omv_i2c_t *i3c, uint8_t cmd) {
|
||||
int ret = 0;
|
||||
ret |= omv_i3c_write_bytes(i3c, 0, &cmd, 1, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
int omv_i3c_readb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t *reg_data) {
|
||||
int ret = 0;
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, ®_addr, 1, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i3c_read_bytes(i3c, tgt_addr, reg_data, 1, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_writeb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {reg_addr, reg_data};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_readb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t *reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {(reg_addr >> 8), reg_addr};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i3c_read_bytes(i3c, tgt_addr, reg_data, 1, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_writeb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {(reg_addr >> 8), reg_addr, reg_data};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 3, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_readw(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t *reg_data) {
|
||||
int ret = 0;
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, ®_addr, 1, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i3c_read_bytes(i3c, tgt_addr, (uint8_t *) reg_data, 2, OMV_I2C_XFER_NO_FLAGS);
|
||||
*reg_data = (*reg_data << 8) | (*reg_data >> 8);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_writew(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {reg_addr, (reg_data >> 8), reg_data};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 3, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_readw2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t *reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {(reg_addr >> 8), reg_addr};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i3c_read_bytes(i3c, tgt_addr, (uint8_t *) reg_data, 2, OMV_I2C_XFER_NO_FLAGS);
|
||||
*reg_data = (*reg_data << 8) | (*reg_data >> 8);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int omv_i3c_writew2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t reg_data) {
|
||||
int ret = 0;
|
||||
uint8_t buf[] = {(reg_addr >> 8), reg_addr, (reg_data >> 8), reg_data};
|
||||
ret |= omv_i3c_write_bytes(i3c, tgt_addr, buf, 4, OMV_I2C_XFER_NO_FLAGS);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int omv_i3c_check_transfer(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len) {
|
||||
uint8_t addr = tgt_addr >> 1;
|
||||
|
||||
if (!buf || !len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (len > I3C_MAX_DATA_BUF_SIZE) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return omv_i3c_get_addr_pos(i3c, addr);
|
||||
}
|
||||
|
||||
int omv_i3c_read_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags) {
|
||||
int32_t index;
|
||||
i3c_xfer_t xfer = {0};
|
||||
I3C_Type *base = (I3C_Type *) i3c->inst;
|
||||
|
||||
index = omv_i3c_check_transfer(i3c, tgt_addr, buf, len);
|
||||
if (index < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
xfer.error = 0U;
|
||||
xfer.tx_buf = NULL;
|
||||
xfer.tx_len = 0U;
|
||||
xfer.xfer_cmd.addr_index = index;
|
||||
xfer.xfer_cmd.data_len = len;
|
||||
xfer.rx_len = len;
|
||||
|
||||
xfer.rx_buf = buf;
|
||||
|
||||
/* Invoke master receive api */
|
||||
if (flags & (OMV_I2C_XFER_NO_STOP | OMV_I2C_XFER_SUSPEND)) {
|
||||
i3c_master_rx_blocking(base, &xfer);
|
||||
} else {
|
||||
i3c_master_rx(base, &xfer);
|
||||
}
|
||||
|
||||
if (omv_i3c_transfer_wait(base, &xfer, I3C_XFER_TIMEOUT) != 0) {
|
||||
omv_i3c_transfer_end(base);
|
||||
return -1;
|
||||
}
|
||||
|
||||
// if (xfer.rx_buf) {
|
||||
// for (uint32_t i = 0, dr = 0; i < xfer.rx_len; i++, dr >>= 8) {
|
||||
// if ((i % 4) == 0) {
|
||||
// dr = base->I3C_RX_DATA_PORT;
|
||||
// }
|
||||
// xfer.rx_buf[i] = dr & 0xFF;
|
||||
// }
|
||||
// }
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_write_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags) {
|
||||
int32_t index;
|
||||
i3c_xfer_t xfer = {0};
|
||||
I3C_Type *base = (I3C_Type *) i3c->inst;
|
||||
|
||||
index = omv_i3c_check_transfer(i3c, tgt_addr, buf, len);
|
||||
if (index < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
xfer.error = 0U;
|
||||
xfer.rx_buf = NULL;
|
||||
xfer.rx_len = 0U;
|
||||
xfer.xfer_cmd.addr_index = index;
|
||||
xfer.xfer_cmd.data_len = len;
|
||||
|
||||
xfer.tx_buf = buf;
|
||||
xfer.tx_len = len;
|
||||
|
||||
/* Invoke master send api */
|
||||
if (flags & (OMV_I2C_XFER_NO_STOP | OMV_I2C_XFER_SUSPEND)) {
|
||||
i3c_master_tx_blocking(base, &xfer);
|
||||
} else {
|
||||
i3c_master_tx(base, &xfer);
|
||||
}
|
||||
|
||||
if (omv_i3c_transfer_wait(base, &xfer, I3C_XFER_TIMEOUT) != 0) {
|
||||
omv_i3c_transfer_end(base);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int omv_i3c_pulse_scl(omv_i2c_t *i3c) {
|
||||
if (i3c->initialized && i3c->scl_pin) {
|
||||
omv_i3c_deinit(i3c);
|
||||
omv_gpio_config(i3c->scl_pin, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
// Pulse SCL to recover stuck device.
|
||||
for (int i = 0; i < 1000; i++) {
|
||||
omv_gpio_write(i3c->scl_pin, 1);
|
||||
mp_hal_delay_us(10);
|
||||
omv_gpio_write(i3c->scl_pin, 0);
|
||||
mp_hal_delay_us(10);
|
||||
}
|
||||
omv_i3c_init(i3c, i3c->id, i3c->speed);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
55
ports/alif/omv_i3c.h
Normal file
55
ports/alif/omv_i3c.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (C) 2013-2024 OpenMV, LLC.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* I3C bus abstraction layer.
|
||||
*/
|
||||
#ifndef __OMV_I3C_H__
|
||||
#define __OMV_I3C_H__
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "omv_i2c.h"
|
||||
|
||||
// Transfer speeds
|
||||
typedef enum _omv_i3c_speed {
|
||||
OMV_I3C_SPEED_SDR = (0U),
|
||||
OMV_I3C_SPEED_HDR = (1U)
|
||||
} omv_i3c_speed_t;
|
||||
|
||||
int omv_i3c_init(omv_i2c_t *i3c, uint32_t bus_id, uint32_t speed);
|
||||
int omv_i3c_deinit(omv_i2c_t *i3c);
|
||||
int omv_i3c_assign(omv_i2c_t *i3c, uint8_t static_addr, uint8_t *dyn_addr);
|
||||
int omv_i3c_scan_assign(omv_i2c_t *i3c, uint8_t *list, uint8_t size);
|
||||
int omv_i3c_enable(omv_i2c_t *i3c, bool enable);
|
||||
int omv_i3c_gencall(omv_i2c_t *i3c, uint8_t cmd);
|
||||
int omv_i3c_pulse_scl(omv_i2c_t *i3c);
|
||||
int omv_i3c_readb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t *reg_data);
|
||||
int omv_i3c_writeb(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint8_t reg_data);
|
||||
int omv_i3c_readb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t *reg_data);
|
||||
int omv_i3c_writeb2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint8_t reg_data);
|
||||
int omv_i3c_readw(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t *reg_data);
|
||||
int omv_i3c_writew(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t reg_addr, uint16_t reg_data);
|
||||
int omv_i3c_readw2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t *reg_data);
|
||||
int omv_i3c_writew2(omv_i2c_t *i3c, uint8_t tgt_addr, uint16_t reg_addr, uint16_t reg_data);
|
||||
int omv_i3c_read_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags);
|
||||
int omv_i3c_write_bytes(omv_i2c_t *i3c, uint8_t tgt_addr, uint8_t *buf, int len, uint32_t flags);
|
||||
#endif // __OMV_I3C_H__
|
||||
@ -2,12 +2,12 @@
|
||||
# Copyright (c) 2013-2025 OpenMV LLC. All rights reserved.
|
||||
# https://github.com/openmv/openmv/blob/master/LICENSE
|
||||
#
|
||||
# This example shows off Google's MediaPipe BlazeFace face detection model.
|
||||
# This example shows off Google's MediaPipe Face Detection model.
|
||||
|
||||
import csi
|
||||
import time
|
||||
import ml
|
||||
from ml.postprocessing import mediapipe_face_detection_postprocess
|
||||
from ml.postprocessing.mediapipe import BlazeFace
|
||||
|
||||
# Initialize the sensor.
|
||||
csi0 = csi.CSI()
|
||||
@ -17,25 +17,22 @@ csi0.framesize(csi.VGA)
|
||||
csi0.window((400, 400))
|
||||
|
||||
# Load built-in face detection model
|
||||
model = ml.Model("/rom/blazeface_front_128.tflite")
|
||||
model = ml.Model("/rom/blazeface_front_128.tflite", postprocess=BlazeFace(threshold=0.4))
|
||||
print(model)
|
||||
|
||||
# Create the face detection post-processor. This post-processor dynamically
|
||||
# generates anchors for the model input size which should only be done once.
|
||||
face_detection_postprocess = mediapipe_face_detection_postprocess(threshold=0.6)
|
||||
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
img = csi0.snapshot()
|
||||
|
||||
# faces is a list of ((x, y, w, h), score, keypoints) tuples
|
||||
faces = model.predict([img], callback=face_detection_postprocess)
|
||||
faces = model.predict([img])
|
||||
|
||||
# Draw bounding boxes around the detected faces and keypoints.
|
||||
if faces:
|
||||
for r, score, keypoints in faces[0]:
|
||||
ml.utils.draw_predictions(img, [r], ["face"], [(0, 0, 255)], format=None)
|
||||
ml.utils.draw_predictions(img, [r], ("face",), ((0, 0, 255),), format=None)
|
||||
|
||||
# keypoints is a ndarray of shape (6, 2)
|
||||
# 0 - right eye (x, y)
|
||||
# 1 - left eye (x, y)
|
||||
@ -43,7 +40,6 @@ while True:
|
||||
# 3 - mouth (x, y)
|
||||
# 4 - right ear (x, y)
|
||||
# 5 - left ear (x, y)
|
||||
for kp in keypoints.tolist():
|
||||
img.draw_circle(int(kp[0]), int(kp[1]), 4, color=(255, 0, 0))
|
||||
ml.utils.draw_keypoints(img, keypoints, color=(255, 0, 0))
|
||||
|
||||
print(clock.fps(), "fps")
|
||||
@ -25,12 +25,6 @@ print(model)
|
||||
# Line connections between hand joints for drawing the hand skeleton.
|
||||
palm_lines = ((0, 1), (1, 2), (2, 3), (3, 4), (4, 0), (0, 5), (5, 6))
|
||||
|
||||
# Visualization parameters.
|
||||
palm_labels = ["palm"]
|
||||
palm_colors = [(0, 0, 255)]
|
||||
kp_color = (255, 0, 0)
|
||||
line_color = (0, 255, 0)
|
||||
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
@ -42,7 +36,7 @@ while True:
|
||||
# Draw bounding boxes around the detected palms and keypoints.
|
||||
if palms:
|
||||
for r, score, keypoints in palms[0]:
|
||||
ml.utils.draw_predictions(img, [r], palm_labels, palm_colors, format=None)
|
||||
ml.utils.draw_predictions(img, [r], ("palm",), ((0, 0, 255),), format=None)
|
||||
|
||||
# keypoints is a ndarray of shape (7, 2)
|
||||
# 0 - wrist (x, y)
|
||||
@ -55,6 +49,6 @@ while True:
|
||||
#
|
||||
# mcp = Metacarpophalangeal Joint - the knuckle
|
||||
# cmc = Carpometacarpal Joint - the base of the thumb
|
||||
ml.utils.draw_skeleton(img, keypoints, palm_lines, kp_color=kp_color, line_color=line_color)
|
||||
ml.utils.draw_skeleton(img, keypoints, palm_lines, kp_color=(255, 0, 0), line_color=(0, 255, 0))
|
||||
|
||||
print(clock.fps(), "fps")
|
||||
|
||||
@ -33,11 +33,6 @@ hand_lines = ((0, 1), (1, 2), (2, 3), (3, 4), (0, 5), (5, 6), (6, 7), (7, 8),
|
||||
(5, 9), (9, 10), (10, 11), (11, 12), (9, 13), (13, 14), (14, 15), (15, 16),
|
||||
(13, 17), (17, 18), (18, 19), (19, 20), (0, 17))
|
||||
|
||||
# Visualization parameters.
|
||||
palm_colors = [(0, 0, 255)]
|
||||
kp_color = (255, 0, 0)
|
||||
line_color = (0, 255, 0)
|
||||
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
@ -61,7 +56,7 @@ while True:
|
||||
# Draw bounding boxes around the detected hands and keypoints.
|
||||
for i, detections in enumerate(hands):
|
||||
for r, score, keypoints in detections:
|
||||
ml.utils.draw_predictions(img, [r], ["right" if i else "left"], palm_colors, format=None)
|
||||
ml.utils.draw_predictions(img, [r], ("right",) if i else ("left",), ((0, 0, 255),), format=None)
|
||||
|
||||
# keypoints: ndarray (21, 3) of hand joints (x, y, z)
|
||||
# Indices follow MediaPipe convention:
|
||||
@ -72,6 +67,6 @@ while True:
|
||||
# Ring: 13 mcp, 14 pip, 15 dip, 16 tip
|
||||
# Pinky: 17 mcp, 18 pip, 19 dip, 20 tip
|
||||
# (cmc=base, mcp=knuckle, pip=mid, dip=distal, ip=thumb joint, tip=fingertip)
|
||||
ml.utils.draw_skeleton(img, keypoints, hand_lines, kp_color=kp_color, line_color=line_color)
|
||||
ml.utils.draw_skeleton(img, keypoints, hand_lines, kp_color=(255, 0, 0), line_color=(0, 255, 0))
|
||||
|
||||
print(clock.fps(), "fps")
|
||||
|
||||
@ -33,11 +33,6 @@ hand_lines = ((0, 1), (1, 2), (2, 3), (3, 4), (0, 5), (5, 6), (6, 7), (7, 8),
|
||||
(5, 9), (9, 10), (10, 11), (11, 12), (9, 13), (13, 14), (14, 15), (15, 16),
|
||||
(13, 17), (17, 18), (18, 19), (19, 20), (0, 17))
|
||||
|
||||
# Visualization parameters.
|
||||
palm_colors = [(0, 0, 255)]
|
||||
kp_color = (255, 0, 0)
|
||||
line_color = (0, 255, 0)
|
||||
|
||||
# Tracking vars.
|
||||
n = None
|
||||
|
||||
@ -71,7 +66,7 @@ while True:
|
||||
# Draw bounding boxes around the detected hands and keypoints.
|
||||
for i, detections in enumerate(hands):
|
||||
for r, score, keypoints in detections:
|
||||
ml.utils.draw_predictions(img, [r], ["right" if i else "left"], [(0, 0, 255)], format=None)
|
||||
ml.utils.draw_predictions(img, [r], ("right",) if i else ("left",), ((0, 0, 255),), format=None)
|
||||
|
||||
# keypoints: ndarray (21, 3) of hand joints (x, y, z)
|
||||
# Indices follow MediaPipe convention:
|
||||
@ -82,7 +77,7 @@ while True:
|
||||
# Ring: 13 mcp, 14 pip, 15 dip, 16 tip
|
||||
# Pinky: 17 mcp, 18 pip, 19 dip, 20 tip
|
||||
# (cmc=base, mcp=knuckle, pip=mid, dip=distal, ip=thumb joint, tip=fingertip)
|
||||
ml.utils.draw_skeleton(img, keypoints, hand_lines, kp_color=kp_color, line_color=line_color)
|
||||
ml.utils.draw_skeleton(img, keypoints, hand_lines, kp_color=(255, 0, 0), line_color=(0, 255, 0))
|
||||
|
||||
# Center new_wider_rect on hand for tracking
|
||||
new_wider_rect = (r[0] + (r[2] // 2) - (wider_rect[2] // 2),
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
import sensor
|
||||
import time
|
||||
import ml
|
||||
from ml.postprocessing import fomo_postprocess
|
||||
from ml.postprocessing.edgeimpulse import Fomo
|
||||
import math
|
||||
|
||||
sensor.reset() # Reset and initialize the sensor.
|
||||
@ -19,7 +19,7 @@ sensor.set_windowing((240, 240)) # Set 240x240 window.
|
||||
sensor.skip_frames(time=2000) # Let the camera adjust.
|
||||
|
||||
# Load built-in FOMO face detection model
|
||||
model = ml.Model("/rom/fomo_face_detection.tflite")
|
||||
model = ml.Model("/rom/fomo_face_detection.tflite", postprocess=Fomo(threshold=0.4))
|
||||
print(model)
|
||||
|
||||
# Alternatively, models can be loaded from the filesystem storage.
|
||||
@ -39,10 +39,9 @@ colors = [ # Add more colors if you are detecting more than 7 types of classes
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
|
||||
img = sensor.snapshot()
|
||||
|
||||
for i, detection_list in enumerate(model.predict([img], callback=fomo_postprocess())):
|
||||
for i, detection_list in enumerate(model.predict([img])):
|
||||
if i == 0:
|
||||
continue # background class
|
||||
if len(detection_list) == 0:
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
# This work is licensed under the MIT license.
|
||||
# Copyright (c) 2013-2025 OpenMV LLC. All rights reserved.
|
||||
# https://github.com/openmv/openmv/blob/master/LICENSE
|
||||
#
|
||||
# TensorFlow Lite YOLO V2 Example
|
||||
#
|
||||
# This example runs a YOLO V2 object detection model.
|
||||
# Please see OpenMV IDE's model zoo for example yolo v2 models.
|
||||
#
|
||||
# For more information on YOLO V2, please see:
|
||||
# https://github.com/STMicroelectronics/stm32ai-modelzoo/tree/main/object_detection/tiny_yolo_v2
|
||||
#
|
||||
# NOTE: This exaxmple requires an OpenMV Cam with an NPU like the AE3 or N6 to run real-time.
|
||||
|
||||
import csi
|
||||
import time
|
||||
import ml
|
||||
from ml.postprocessing.darknet import YoloV2
|
||||
|
||||
# Initialize the sensor.
|
||||
csi0 = csi.CSI()
|
||||
csi0.reset()
|
||||
csi0.pixformat(csi.RGB565)
|
||||
csi0.framesize(csi.VGA)
|
||||
csi0.window((400, 400))
|
||||
|
||||
# Load YOLO V2 model from ROM FS.
|
||||
model = ml.Model("/rom/<model_file_name>", postprocess=YoloV2(threshold=0.4))
|
||||
print(model)
|
||||
|
||||
# Visualization parameters.
|
||||
n = len(model.labels)
|
||||
model_class_colors = [(int(255 * i // n), int(255 * (n - i - 1) // n), 255) for i in range(n)]
|
||||
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
img = csi0.snapshot()
|
||||
|
||||
# boxes is a list of list per class of ((x, y, w, h), score) tuples
|
||||
boxes = model.predict([img])
|
||||
|
||||
# Draw bounding boxes around the detected objects
|
||||
for i, class_detections in enumerate(boxes):
|
||||
rects = [r for r, score in class_detections]
|
||||
labels = [model.labels[i] for j in range(len(rects))]
|
||||
colors = [model_class_colors[i] for j in range(len(rects))]
|
||||
ml.utils.draw_predictions(img, rects, labels, colors, format=None)
|
||||
|
||||
print(clock.fps(), "fps")
|
||||
@ -0,0 +1,50 @@
|
||||
# This work is licensed under the MIT license.
|
||||
# Copyright (c) 2013-2025 OpenMV LLC. All rights reserved.
|
||||
# https://github.com/openmv/openmv/blob/master/LICENSE
|
||||
#
|
||||
# TensorFlow Lite YOLO V5 Example
|
||||
#
|
||||
# This example runs a YOLO V5 object detection model.
|
||||
# Please see OpenMV IDE's model zoo for example yolo v5 models.
|
||||
#
|
||||
# You can train your own custom YOLOV5 models using Edge Impulse:
|
||||
# https://github.com/edgeimpulse/ml-block-yolov5
|
||||
#
|
||||
# NOTE: This exaxmple requires an OpenMV Cam with an NPU like the AE3 or N6 to run real-time.
|
||||
|
||||
import csi
|
||||
import time
|
||||
import ml
|
||||
from ml.postprocessing.ultralytics import YoloV5
|
||||
|
||||
# Initialize the sensor.
|
||||
csi0 = csi.CSI()
|
||||
csi0.reset()
|
||||
csi0.pixformat(csi.RGB565)
|
||||
csi0.framesize(csi.VGA)
|
||||
csi0.window((400, 400))
|
||||
|
||||
# Load YOLO V5 model from ROM FS.
|
||||
model = ml.Model("/rom/<model_file_name>", postprocess=YoloV5(threshold=0.4))
|
||||
print(model)
|
||||
|
||||
# Visualization parameters.
|
||||
n = len(model.labels)
|
||||
model_class_colors = [(int(255 * i // n), int(255 * (n - i - 1) // n), 255) for i in range(n)]
|
||||
|
||||
clock = time.clock()
|
||||
while True:
|
||||
clock.tick()
|
||||
img = csi0.snapshot()
|
||||
|
||||
# boxes is a list of list per class of ((x, y, w, h), score) tuples
|
||||
boxes = model.predict([img])
|
||||
|
||||
# Draw bounding boxes around the detected objects
|
||||
for i, class_detections in enumerate(boxes):
|
||||
rects = [r for r, score in class_detections]
|
||||
labels = [model.labels[i] for j in range(len(rects))]
|
||||
colors = [model_class_colors[i] for j in range(len(rects))]
|
||||
ml.utils.draw_predictions(img, rects, labels, colors, format=None)
|
||||
|
||||
print(clock.fps(), "fps")
|
||||
@ -47,7 +47,6 @@ class YoloV2:
|
||||
def __init__(self, threshold=0.6, anchors=None, nms_threshold=0.1, nms_sigma=0.1):
|
||||
self.threshold = threshold
|
||||
self.anchors = anchors
|
||||
self.anchors_len = len(self.anchors)
|
||||
self.nms_threshold = nms_threshold
|
||||
self.nms_sigma = nms_sigma
|
||||
|
||||
@ -58,6 +57,8 @@ class YoloV2:
|
||||
[5.55170, 9.30660],
|
||||
[9.72600, 11.1422]])
|
||||
|
||||
self.anchors_len = len(self.anchors)
|
||||
|
||||
def __call__(self, model, inputs, outputs):
|
||||
|
||||
def softmax(x):
|
||||
|
||||
Loading…
Reference in New Issue
Block a user