mirror of
https://github.com/openmv/openmv.git
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135 lines
3.0 KiB
INI
135 lines
3.0 KiB
INI
[System_Config.RTSS_HP_SRAM_MRAM]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=OffChipFlash
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Sram_clock_scale=0.762
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Sram_burst_length=8
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Sram_read_latency=29
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Sram_write_latency=29
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OffChipFlash_clock_scale=0.121
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OffChipFlash_burst_length=16
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OffChipFlash_read_latency=60
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OffChipFlash_write_latency=60
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[System_Config.RTSS_HP_SRAM_OSPI]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=OffChipFlash
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Sram_clock_scale=0.762
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Sram_burst_length=8
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Sram_read_latency=29
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Sram_write_latency=29
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OffChipFlash_clock_scale=0.052
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OffChipFlash_burst_length=16
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OffChipFlash_read_latency=108
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OffChipFlash_write_latency=108
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[System_Config.RTSS_HE_SRAM_MRAM]
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core_clock=160e6
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axi0_port=Sram
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axi1_port=OffChipFlash
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Sram_clock_scale=1.0
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Sram_burst_length=8
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Sram_read_latency=13
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Sram_write_latency=13
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OffChipFlash_clock_scale=0.303
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OffChipFlash_burst_length=16
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OffChipFlash_read_latency=24
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OffChipFlash_write_latency=24
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[System_Config.RTSS_HE_SRAM_Only]
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core_clock=160e6
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axi0_port=Sram
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axi1_port=OnChipFlash
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Sram_clock_scale=1.0
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Sram_burst_length=8
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Sram_read_latency=13
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Sram_write_latency=13
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OnChipFlash_clock_scale=1.0
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OnChipFlash_burst_length=8
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OnChipFlash_read_latency=13
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OnChipFlash_write_latency=13
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[System_Config.RTSS_HP_DTCM_Only]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=OnChipFlash
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Sram_clock_scale=0.889
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Sram_burst_length=32
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Sram_read_latency=5
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Sram_write_latency=5
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OnChipFlash_clock_scale=0.889
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OnChipFlash_burst_length=32
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OnChipFlash_read_latency=5
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OnChipFlash_write_latency=5
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[System_Config.RTSS_HE_DTCM_Only]
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core_clock=160e6
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axi0_port=Sram
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axi1_port=OnChipFlash
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Sram_clock_scale=0.889
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Sram_burst_length=32
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Sram_read_latency=5
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Sram_write_latency=5
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OnChipFlash_clock_scale=0.889
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OnChipFlash_burst_length=32
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OnChipFlash_read_latency=5
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OnChipFlash_write_latency=5
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[System_Config.RTSS_HP_DTCM_MRAM]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=OffChipFlash
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Sram_clock_scale=0.889
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Sram_burst_length=32
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Sram_read_latency=5
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Sram_write_latency=5
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OffChipFlash_clock_scale=0.118
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OffChipFlash_burst_length=64
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OffChipFlash_read_latency=60
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OffChipFlash_write_latency=60
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[System_Config.RTSS_HP_DTCM_Modem]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=OffChipFlash
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Sram_clock_scale=0.889
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Sram_burst_length=32
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Sram_read_latency=5
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Sram_write_latency=5
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OffChipFlash_clock_scale=0.200
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OffChipFlash_burst_length=64
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OffChipFlash_read_latency=53
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OffChipFlash_write_latency=53
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[System_Config.RTSS_HP_DTCM_SRAM]
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core_clock=400e6
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axi0_port=Sram
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axi1_port=Dram
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Sram_clock_scale=1.0
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Sram_burst_length=16
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Sram_read_latency=5
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Sram_write_latency=5
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Dram_clock_scale=0.762
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Dram_burst_length=32
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Dram_read_latency=29
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Dram_write_latency=29
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; -----------------------------------------------------------------------------
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; Memory Mode
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; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
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; The non-SRAM memory is assumed to be read-only
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; This is appropriate for the SRAM_MRAM or DTCM_MRAM configs
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[Memory_Mode.Shared_Sram]
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const_mem_area=Axi1
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arena_mem_area=Axi0
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cache_mem_area=Axi0
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; DTCM Cache
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; This is appropriate for the DTCM_SRAM configs
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[Memory_Mode.Dtcm_Cache]
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const_mem_area=Axi1
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arena_mem_area=Axi1
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cache_mem_area=Axi0
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